[coreboot-gerrit] Change in coreboot[master]: nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h>

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49536 )

Change subject: nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h>
......................................................................

nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h>

Also rename 'reg' to 'reg32'.

Change-Id: Ie8dd238a8f10daad9653f44b3ada329c3ede58fe
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49536
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/northbridge/intel/haswell/bootblock.c
1 file changed, 4 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index 64e2258..0bb8ae2 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -1,9 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/bootblock.h>
+#include <arch/pci_io_cfg.h>
 #include <assert.h>
-#include <device/pci_ops.h>
 #include <types.h>
+
 #include "haswell.h"

static uint32_t encode_pciexbar_length(void)
@@ -28,7 +29,7 @@
     *
     * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
     */
-	const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+	const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
    pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
-	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
+	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
 }