Attention is currently required from: Furquan Shaikh, Mariusz Szafrański, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Angel Pons, Michal Motyl, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Mariusz Szafrański, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Angel Pons, Michal Motyl, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51767
to look at the new patch set (#8).
Change subject: soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h ......................................................................
soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h
Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. An advanced GPIO PM capabilities has been introduced in CNP PCH.
Refer to 'include/intelblock/gpio.h' for details.
Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to move MISCCFG bit definitions from intelblock/gpio.h to soc/gpio.h so that each SoC can provide the definition of MISCCFG_GPIO_PM_CONFIG_BITS as per the hardware support.
TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable)
With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable)
Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/mainboard.asl M src/soc/intel/alderlake/acpi/gpio.asl M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/include/soc/gpio.h M src/soc/intel/apollolake/include/soc/gpio.h M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/cannonlake/include/soc/gpio.h M src/soc/intel/common/acpi/gpio.asl M src/soc/intel/common/acpi/platform.asl M src/soc/intel/common/block/acpi/acpi/pep.asl M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/denverton_ns/include/soc/gpio.h M src/soc/intel/elkhartlake/chip.c M src/soc/intel/elkhartlake/include/soc/gpio.h M src/soc/intel/icelake/chip.c M src/soc/intel/icelake/include/soc/gpio.h M src/soc/intel/jasperlake/chip.c M src/soc/intel/jasperlake/include/soc/gpio.h M src/soc/intel/skylake/include/soc/gpio.h M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/gpio.h M src/soc/intel/xeon_sp/include/soc/gpio.h 26 files changed, 89 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/51767/8