Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41674 )
Change subject: soc/intel/common/block/sata: Fix SATA detection issue between Ports 3-7 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41674/4/src/soc/intel/common/block/... File src/soc/intel/common/block/sata/sata.c:
https://review.coreboot.org/c/coreboot/+/41674/4/src/soc/intel/common/block/... PS4, Line 12: #define SATA_PCI_CFG_PORT_CTL_STS 0x92 This changed to 0x94 with Cannon Point PCH.
SOC_AHCI_PORT_IMPLEMENTED_INVERTED covers this up. Pre CNP, the code configured Port Control and Status (PCS), but for later generations it writes into Port Mapping (MAP) by accident. MAP contains disable bits, hence the INVERTED option was necessary to not break things, but PCS is still not written.
A hunch tells me that the whole driver here is not necessary for platforms where FSP already sets PCS. We keep patching this code, but only so that it doesn't break things. Does it do anything useful, though? We could dump the PCS state to figure out.