Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83679?usp=email )
Change subject: soc/inte/{adl,mtl}: Move ASPM helper functions to common ......................................................................
soc/inte/{adl,mtl}: Move ASPM helper functions to common
The ASPM helper functions are the same for all Intel SOCs since Skylake, so move them to common code.
Change-Id: Ic6876e920d75abbbbb27d4ce3a4f2c08a8db9410 Signed-off-by: Sean Rhodes sean@starlabs.systems Reviewed-on: https://review.coreboot.org/c/coreboot/+/83679 Reviewed-by: Kapil Porwal kapilporwal@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/common/Kconfig.common A src/soc/intel/common/block/aspm/Kconfig A src/soc/intel/common/block/aspm/Makefile.mk A src/soc/intel/common/block/aspm/aspm.c A src/soc/intel/common/block/include/intelblocks/aspm.h M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/fsp_params.c 9 files changed, 164 insertions(+), 187 deletions(-)
Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 15f347f..4f374eb 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -51,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ + select SOC_INTEL_COMMON_BLOCK_ASPM select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI @@ -84,6 +85,7 @@ select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET select SOC_INTEL_CRASHLOG if MAINBOARD_HAS_CHROMEOS + select HAS_INTEL_CPU_ROOT_PORTS select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON && !BOARD_GOOGLE_BROX_COMMON select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8a03b05..cbfd223d 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -18,6 +18,7 @@ #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> #include <gpio.h> +#include <intelblocks/aspm.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/mp_init.h> @@ -466,123 +467,6 @@ return config; }
-/* - * The PCIe RP ASPM and PCIe L1 Substate UPDs follow the PCI Express Base - * Specification 1.1. The UPDs and their default values are consistent - * from Skylake through Meteor Lake. However, the default for CPU ports - * differs from PCH ports. Use auto and maximum unless overwritten - * to make the behaviour consistent. - * - * +-------------------+--------------------------+-----------+-----------+ - * | Setting | Option | PCH Ports | CPU Ports | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpEnableCpm | Disabled | [Default] | [Default] | - * | | Enabled | | | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpAspm | PchPcieAspmDisabled | | | - * | | PchPcieAspmL0s | | | - * | | PchPcieAspmL1 | | | - * | | PchPcieAspmL0sL1 | | [Default] | - * | | PchPcieAspmAutoConfig | [Default] | | - * | | PchPcieAspmMax | | | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpL1Substates | Disabled | | | - * | | PchPcieL1SubstatesL1_1 | | | - * | | PchPcieL1SubstatesL1_1_2 | | [Default] | - * | | PchPcieL1SubstatesMax | [Default] | | - * |-------------------|--------------------------|-----------|-----------| - * | PchPcieRpPcieSpeed| PchPcieRpPcieSpeedAuto | [Default] | | - * | | PchPcieRpPcieSpeedGen1 | | | - * | | PchPcieRpPcieSpeedGen2 | | | - * | | PchPcieRpPcieSpeedGen3 | | | - * | | PchPcieRpPcieSpeedGen4 | | | - * +-------------------+--------------------------+-----------+-----------+ - */ - -static unsigned int adl_aspm_control_to_upd(enum ASPM_control aspm_control) -{ - /* Disable without Kconfig selected */ - if (!CONFIG(PCIEXP_ASPM)) - return UPD_INDEX(ASPM_DISABLE); - - /* Use auto unless overwritten */ - if (!aspm_control) - return UPD_INDEX(ASPM_AUTO); - - return UPD_INDEX(aspm_control); -} - -static unsigned int adl_l1ss_control_to_upd(enum L1_substates_control l1_substates_control) -{ - /* Disable without Kconfig selected */ - if (!CONFIG(PCIEXP_ASPM)) - return UPD_INDEX(L1_SS_DISABLED); - - /* Don't enable UPD if Kconfig not set */ - if (!CONFIG(PCIEXP_L1_SUB_STATE)) - return UPD_INDEX(L1_SS_DISABLED); - - /* L1 Substate should be disabled in compliance mode */ - if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) - return UPD_INDEX(L1_SS_DISABLED); - - /* Use maximum unless overwritten */ - if (!l1_substates_control) - return UPD_INDEX(L1_SS_L1_2); - - return UPD_INDEX(l1_substates_control); -} - -static unsigned int adl_pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control) -{ - /* Use auto unless overwritten */ - if (!pcie_speed_control) - return UPD_INDEX(SPEED_AUTO); - - return UPD_INDEX(pcie_speed_control); -} - -static void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, - const struct pcie_rp_config *rp_cfg, - unsigned int index) -{ - s_cfg->PcieRpEnableCpm[index] = - get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); - s_cfg->PcieRpAspm[index] = - adl_aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); - s_cfg->PcieRpL1Substates[index] = - adl_l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); - s_cfg->PcieRpPcieSpeed[index] = - adl_pcie_speed_control_to_upd(get_uint_option("pciexp_speed", rp_cfg->pcie_rp_pcie_speed)); -} - -/* - * Starting with Alder Lake, UPDs for Clock Power Management were - * introduced for the CPU root ports. - * - * CpuPcieClockGating: - * Disabled - * Enabled [Default] - * - * CpuPciePowerGating - * Disabled - * Enabled [Default] - * - */ -static void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, - const struct pcie_rp_config *rp_cfg, - unsigned int index) -{ - bool pciexp_clk_pm = get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); - s_cfg->CpuPcieRpEnableCpm[index] = pciexp_clk_pm; - s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm; - s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm; - s_cfg->CpuPcieRpAspm[index] = - adl_aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); - s_cfg->CpuPcieRpL1Substates[index] = - adl_l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); -} - /* This function returns the VccIn Aux Imon IccMax values for ADL and RPL SKU's */ static uint16_t get_vccin_aux_imon_iccmax(const struct soc_intel_alderlake_config *config) diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index 7ce93d4..7cd5743 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -151,6 +151,11 @@ This will result in a BERT table being populated containing a PMC crashlog record on every boot.
+config HAS_INTEL_CPU_ROOT_PORTS + def_bool n + help + Enables helper functions for CPU root ports alongside PCH root ports. + config SOC_INTEL_IOE_DIE_SUPPORT def_bool n help diff --git a/src/soc/intel/common/block/aspm/Kconfig b/src/soc/intel/common/block/aspm/Kconfig new file mode 100644 index 0000000..bab1357 --- /dev/null +++ b/src/soc/intel/common/block/aspm/Kconfig @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_INTEL_COMMON_BLOCK_ASPM + bool + help + Intel Processor common ASPM support diff --git a/src/soc/intel/common/block/aspm/Makefile.mk b/src/soc/intel/common/block/aspm/Makefile.mk new file mode 100644 index 0000000..fe6c71d --- /dev/null +++ b/src/soc/intel/common/block/aspm/Makefile.mk @@ -0,0 +1,2 @@ +## SPDX-License-Identifier: GPL-2.0-only +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ASPM) += aspm.c diff --git a/src/soc/intel/common/block/aspm/aspm.c b/src/soc/intel/common/block/aspm/aspm.c new file mode 100644 index 0000000..afdf3f6 --- /dev/null +++ b/src/soc/intel/common/block/aspm/aspm.c @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/api.h> +#include <intelblocks/aspm.h> +#include <intelblocks/pcie_rp.h> +#include <option.h> +#include <soc/soc_chip.h> +#include <soc/pcie.h> + +/* + * The PCIe RP ASPM and PCIe L1 Substate UPDs follow the PCI Express Base + * Specification 1.1. The UPDs and their default values are consistent + * from Skylake through Meteor Lake. However, the default for CPU ports + * differs from PCH ports. Use auto and maximum unless overwritten + * to make the behaviour consistent. + * + * +-------------------+--------------------------+-----------+-----------+ + * | Setting | Option | PCH Ports | CPU Ports | + * |-------------------|--------------------------|-----------|-----------| + * | PcieRpEnableCpm | Disabled | [Default] | [Default] | + * | | Enabled | | | + * |-------------------|--------------------------|-----------|-----------| + * | PcieRpAspm | PchPcieAspmDisabled | | | + * | | PchPcieAspmL0s | | | + * | | PchPcieAspmL1 | | | + * | | PchPcieAspmL0sL1 | | [Default] | + * | | PchPcieAspmAutoConfig | [Default] | | + * | | PchPcieAspmMax | | | + * |-------------------|--------------------------|-----------|-----------| + * | PcieRpL1Substates | Disabled | | | + * | | PchPcieL1SubstatesL1_1 | | | + * | | PchPcieL1SubstatesL1_1_2 | | [Default] | + * | | PchPcieL1SubstatesMax | [Default] | | + * |-------------------|--------------------------|-----------|-----------| + * | PchPcieRpPcieSpeed| PchPcieRpPcieSpeedAuto | [Default] | | + * | | PchPcieRpPcieSpeedGen1 | | | + * | | PchPcieRpPcieSpeedGen2 | | | + * | | PchPcieRpPcieSpeedGen3 | | | + * | | PchPcieRpPcieSpeedGen4 | | | + * +-------------------+--------------------------+-----------+-----------+ + */ + +static unsigned int aspm_control_to_upd(enum ASPM_control aspm_control) +{ + /* Disable without Kconfig selected */ + if (!CONFIG(PCIEXP_ASPM)) + return UPD_INDEX(ASPM_DISABLE); + + /* Use auto unless overwritten */ + if (!aspm_control) + return UPD_INDEX(ASPM_AUTO); + + return UPD_INDEX(aspm_control); +} + +static unsigned int l1ss_control_to_upd(enum L1_substates_control l1_substates_control) +{ + /* Disable without Kconfig selected */ + if (!CONFIG(PCIEXP_ASPM)) + return UPD_INDEX(L1_SS_DISABLED); + + /* Don't enable UPD if Kconfig not set */ + if (!CONFIG(PCIEXP_L1_SUB_STATE)) + return UPD_INDEX(L1_SS_DISABLED); + + /* L1 Substate should be disabled in compliance mode */ + if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) + return UPD_INDEX(L1_SS_DISABLED); + + /* Use maximum unless overwritten */ + if (!l1_substates_control) + return UPD_INDEX(L1_SS_L1_2); + + return UPD_INDEX(l1_substates_control); +} + +static unsigned int pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control) +{ + /* Use auto unless overwritten */ + if (!pcie_speed_control) + return UPD_INDEX(SPEED_AUTO); + + return UPD_INDEX(pcie_speed_control); +} + +void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, + const struct pcie_rp_config *rp_cfg, + unsigned int index) +{ + s_cfg->PcieRpEnableCpm[index] = + get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); + s_cfg->PcieRpAspm[index] = + aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); + s_cfg->PcieRpL1Substates[index] = + l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); + s_cfg->PcieRpPcieSpeed[index] = + pcie_speed_control_to_upd(get_uint_option("pciexp_speed", rp_cfg->pcie_rp_pcie_speed)); +} + +#if CONFIG(HAS_INTEL_CPU_ROOT_PORTS) +/* + * Starting with Alder Lake, UPDs for Clock Power Management were + * introduced for the CPU root ports. + * + * CpuPcieClockGating: + * Disabled + * Enabled [Default] + * + * CpuPciePowerGating + * Disabled + * Enabled [Default] + * + */ +void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, + const struct pcie_rp_config *rp_cfg, + unsigned int index) +{ + bool pciexp_clk_pm = get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM)); + s_cfg->CpuPcieRpEnableCpm[index] = pciexp_clk_pm; + s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm; + s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm; + s_cfg->CpuPcieRpAspm[index] = + aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm)); + s_cfg->CpuPcieRpL1Substates[index] = + l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); +} + +#endif // CONFIG(HAS_INTEL_CPU_ROOT_PORTS) diff --git a/src/soc/intel/common/block/include/intelblocks/aspm.h b/src/soc/intel/common/block/include/intelblocks/aspm.h new file mode 100644 index 0000000..297e128 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/aspm.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_ASPM_H +#define SOC_INTEL_COMMON_BLOCK_ASPM_H + +#include <intelblocks/pcie_rp.h> + +void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, + const struct pcie_rp_config *rp_cfg, + unsigned int index); + +#if CONFIG(HAS_INTEL_CPU_ROOT_PORTS) +void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, + const struct pcie_rp_config *rp_cfg, + unsigned int index); +#endif + +#endif /* SOC_INTEL_COMMON_BLOCK_ASPM_H */ diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 73d68df..bc0183d 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -54,6 +54,7 @@ select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ + select SOC_INTEL_COMMON_BLOCK_ASPM select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 3b4fe46..f3fec48 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -16,6 +16,7 @@ #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> #include <option.h> +#include <intelblocks/aspm.h> #include <intelblocks/cse.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> @@ -264,76 +265,6 @@ }
/* - * The PCIe RP ASPM and PCIe L1 Substate UPDs follow the PCI Express Base - * Specification 1.1. The UPDs and their default values are consistent - * from Skylake through Meteor Lake. However, the default for CPU ports - * differs from PCH ports. Use auto and maximum unless overwritten - * to make the behaviour consistent. - * - * +-------------------+--------------------------+-----------+-----------+ - * | Setting | Option | PCH Ports | CPU Ports | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpEnableCpm | Disabled | [Default] | [Default] | - * | | Enabled | | | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpAspm | PchPcieAspmDisabled | | | - * | | PchPcieAspmL0s | | | - * | | PchPcieAspmL1 | | | - * | | PchPcieAspmL0sL1 | | [Default] | - * | | PchPcieAspmAutoConfig | [Default] | | - * | | PchPcieAspmMax | | | - * |-------------------|--------------------------|-----------|-----------| - * | PcieRpL1Substates | Disabled | | | - * | | PchPcieL1SubstatesL1_1 | | | - * | | PchPcieL1SubstatesL1_1_2 | | [Default] | - * | | PchPcieL1SubstatesMax | [Default] | | - * +-------------------+--------------------------+-----------+-----------+ - */ - -static unsigned int mtl_aspm_control_to_upd(enum ASPM_control aspm_control) -{ - /* Disable without Kconfig selected */ - if (!CONFIG(PCIEXP_ASPM)) - return UPD_INDEX(ASPM_DISABLE); - - /* Use auto unless overwritten */ - if (!aspm_control) - return UPD_INDEX(ASPM_AUTO); - - return UPD_INDEX(aspm_control); -} - -static unsigned int mtl_l1ss_control_to_upd(enum L1_substates_control l1_substates_control) -{ - /* Disable without Kconfig selected */ - if (!CONFIG(PCIEXP_ASPM)) - return UPD_INDEX(L1_SS_DISABLED); - - /* Don't enable UPD if Kconfig not set */ - if (!CONFIG(PCIEXP_L1_SUB_STATE)) - return UPD_INDEX(L1_SS_DISABLED); - - /* L1 Substate should be disabled in compliance mode */ - if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) - return UPD_INDEX(L1_SS_DISABLED); - - /* Use maximum unless overwritten */ - if (!l1_substates_control) - return UPD_INDEX(L1_SS_L1_2); - - return UPD_INDEX(l1_substates_control); -} - -static void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg, - const struct pcie_rp_config *rp_cfg, - unsigned int index) -{ - s_cfg->PcieRpEnableCpm[index] = CONFIG(PCIEXP_CLK_PM); - s_cfg->PcieRpAspm[index] = mtl_aspm_control_to_upd(rp_cfg->pcie_rp_aspm); - s_cfg->PcieRpL1Substates[index] = mtl_l1ss_control_to_upd(rp_cfg->PcieRpL1Substates); -} - -/* * ME End of Post configuration * 0 - Disable EOP. * 1 - Send in PEI (Applicable for FSP in API mode)