[coreboot-gerrit] Change in coreboot[master]: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT

[Brandon Breitenstein (Code Review)]

Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
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Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38737/3/src/soc/intel/tigerlake/chi... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38737/3/src/soc/intel/tigerlake/chi... 
PS3, Line 235: USB4/TBT
> should these be structured as an array like ITbtPcieRootPortEn?

This is a different config than ITbtPcieRootPortEn...that one is in Fsps the one that is being changed my this config is in Fspm and is for the bridge not the root port if my understanding of the to configs is correct