HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44106 )
Change subject: src[azalia]: Move common HDA registers to <device/azalia_device.h> ......................................................................
src[azalia]: Move common HDA registers to <device/azalia_device.h>
Change-Id: I9ea191e5076e2f055405dc34d46dbbb8cfb0015e Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/device/azalia_device.c M src/include/device/azalia_device.h M src/soc/intel/common/hda_verb.h M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/lynxpoint/hda_verb.h 9 files changed, 81 insertions(+), 111 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44106/1
diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 1e0cf2f..bd35c8e 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -7,10 +7,6 @@ #include <device/mmio.h> #include <delay.h>
-#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -46,13 +42,13 @@ int count;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) goto no_codec;
/* clear STATESTS bits (BAR + 0xE)[2:0] */ - reg32 = read32(base + 0x0E); + reg32 = read32(base + HDA_STATESTS_REG); reg32 |= 7; - write32(base + 0x0E, reg32); + write32(base + HDA_STATESTS_REG, reg32);
/* Wait for readback of register to * match what was just written to it @@ -61,22 +57,22 @@ do { /* Wait 1ms based on BKDG wait time */ mdelay(1); - reg32 = read32(base + 0x0E); + reg32 = read32(base + HDA_STATESTS_REG); } while ((reg32 != 0) && --count); /* Timeout occurred */ if (!count) goto no_codec;
/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */ - reg32 = read32(base + 0xe); + reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) goto no_codec; @@ -86,7 +82,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "azalia_audio: No codec!\n"); return 0; } @@ -178,12 +174,12 @@ return;
reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32);
if (wait_for_valid(base) == -1) return;
- reg32 = read32(base + 0x64); + reg32 = read32(base + HDA_IR_REG);
/* 2 */ printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32); @@ -200,7 +196,7 @@ if (wait_for_ready(base) == -1) return;
- write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]);
if (wait_for_valid(base) == -1) return; diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 9026091..cc4ce75 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -3,10 +3,20 @@ #ifndef DEVICE_AZALIA_H #define DEVICE_AZALIA_H
-#include <types.h> #include <acpi/acpi.h> #include <device/mmio.h> #include <device/device.h> +#include <stdint.h> + +#define HDA_GCAP_REG 0x00 +#define HDA_GCTL_REG 0x08 +#define HDA_GCTL_CRST (1 << 0) +#define HDA_STATESTS_REG 0x0e +#define HDA_IC_REG 0x60 +#define HDA_IR_REG 0x64 +#define HDA_ICII_REG 0x68 +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1)
void azalia_audio_init(struct device *dev); extern struct device_operations default_azalia_audio_ops; diff --git a/src/soc/intel/common/hda_verb.h b/src/soc/intel/common/hda_verb.h index 9b77ee3..a737289 100644 --- a/src/soc/intel/common/hda_verb.h +++ b/src/soc/intel/common/hda_verb.h @@ -3,18 +3,9 @@ #ifndef _COMMON_HDA_VERB_H_ #define _COMMON_HDA_VERB_H_
+#include <device/azalia_device.h> #include <stdint.h>
-#define HDA_GCAP_REG 0x00 -#define HDA_GCTL_REG 0x08 -#define HDA_GCTL_CRST (1 << 0) -#define HDA_STATESTS_REG 0x0e -#define HDA_IC_REG 0x60 -#define HDA_IR_REG 0x64 -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - int hda_codec_detect(u8 *base); int hda_codec_write(u8 *base, u32 size, const u32 *data); int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data); diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 4f5d8ca..3d4f7ca 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -12,10 +12,6 @@ #include "chip.h" #include "pch.h"
-#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - typedef struct southbridge_intel_bd82x6x_config config_t;
static int set_bits(void *port, u32 mask, u32 val) @@ -52,15 +48,15 @@ u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) goto no_codec;
/* Write back the value once reset bit is set. */ - write16(base + 0x0, - read16(base + 0x0)); + write16(base + HDA_GCAP_REG, + read16(base + HDA_GCAP_REG));
/* Read in Codec location (BAR + 0xe)[2..0]*/ - reg8 = read8(base + 0xe); + reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f; if (!reg8) goto no_codec; @@ -70,7 +66,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } @@ -159,14 +155,14 @@ }
reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32);
if (wait_for_valid(base) == -1) { printk(BIOS_DEBUG, " codec not valid.\n"); return; }
- reg32 = read32(base + 0x64); + reg32 = read32(base + HDA_IR_REG);
/* 2 */ printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); @@ -183,7 +179,7 @@ if (wait_for_ready(base) == -1) return;
- write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]);
if (wait_for_valid(base) == -1) return; @@ -203,7 +199,7 @@ if (wait_for_ready(base) == -1) return;
- write32(base + 0x60, pc_beep_verbs[i]); + write32(base + HDA_IC_REG, pc_beep_verbs[i]);
if (wait_for_valid(base) == -1) return; @@ -268,9 +264,9 @@ /* Codec Initialization Programming Sequence */
/* Take controller out of reset */ - reg32 = read32(base + 0x08); - reg32 |= (1 << 0); - write32(base + 0x08, reg32); + reg32 = read32(base + HDA_GCTL_REG); + reg32 |= HDA_GCTL_CRST; + write32(base + HDA_GCTL_REG, reg32); /* Wait 1ms */ udelay(1000);
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index cea75bd9..9187aa5 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -11,10 +11,6 @@ #include "chip.h" #include "i82801gx.h"
-#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -47,15 +43,15 @@ u32 reg32;
/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/ - reg32 = read32(base + 0xe); + reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) goto no_codec; @@ -65,7 +61,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } @@ -118,9 +114,9 @@ u32 reg32;
/* Send the verb to the codec */ - reg32 = read32(base + 0x68); - reg32 |= (1 << 0) | (1 << 1); - write32(base + 0x68, reg32); + reg32 = read32(base + HDA_ICII_REG); + reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; + write32(base + HDA_ICII_REG, reg32);
/* Use a 50 usec timeout - the Linux kernel uses the same duration */
@@ -149,12 +145,12 @@ return;
reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32);
if (wait_for_valid(base) == -1) return;
- reg32 = read32(base + 0x64); + reg32 = read32(base + HDA_IR_REG);
/* 2 */ printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); @@ -171,7 +167,7 @@ if (wait_for_ready(base) == -1) return;
- write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]);
if (wait_for_valid(base) == -1) return; diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index c954f9c..f0c00b6 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -11,10 +11,6 @@ #include "chip.h" #include "i82801ix.h"
-#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -47,15 +43,15 @@ u32 reg32;
/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/ - reg32 = read32(base + 0xe); + reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) goto no_codec; @@ -65,7 +61,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } @@ -118,9 +114,9 @@ u32 reg32;
/* Send the verb to the codec */ - reg32 = read32(base + 0x68); - reg32 |= (1 << 0) | (1 << 1); - write32(base + 0x68, reg32); + reg32 = read32(base + HDA_ICII_REG); + reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; + write32(base + HDA_ICII_REG, reg32);
/* Use a 50 usec timeout - the Linux kernel uses the same duration */
@@ -149,12 +145,12 @@ return;
reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32);
if (wait_for_valid(base) == -1) return;
- reg32 = read32(base + 0x64); + reg32 = read32(base + HDA_IR_REG);
/* 2 */ printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); @@ -171,7 +167,7 @@ if (wait_for_ready(base) == -1) return;
- write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]);
if (wait_for_valid(base) == -1) return; @@ -191,7 +187,7 @@ if (wait_for_ready(base) == -1) return;
- write32(base + 0x60, pc_beep_verbs[i]); + write32(base + HDA_IC_REG, pc_beep_verbs[i]);
if (wait_for_valid(base) == -1) return; diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index ba20a6a..b53d641 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -11,10 +11,6 @@ #include "chip.h" #include "i82801jx.h"
-#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -47,15 +43,15 @@ u32 reg32;
/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/ - reg32 = read32(base + 0xe); + reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) goto no_codec; @@ -65,7 +61,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } @@ -118,9 +114,9 @@ u32 reg32;
/* Send the verb to the codec */ - reg32 = read32(base + 0x68); - reg32 |= (1 << 0) | (1 << 1); - write32(base + 0x68, reg32); + reg32 = read32(base + HDA_ICII_REG); + reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; + write32(base + HDA_ICII_REG, reg32);
/* Use a 50 usec timeout - the Linux kernel uses the same duration */
@@ -149,12 +145,12 @@ return;
reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32);
if (wait_for_valid(base) == -1) return;
- reg32 = read32(base + 0x64); + reg32 = read32(base + HDA_IR_REG);
/* 2 */ printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); @@ -171,7 +167,7 @@ if (wait_for_ready(base) == -1) return;
- write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]);
if (wait_for_valid(base) == -1) return; @@ -191,7 +187,7 @@ if (wait_for_ready(base) == -1) return;
- write32(base + 0x60, pc_beep_verbs[i]); + write32(base + HDA_IC_REG, pc_beep_verbs[i]);
if (wait_for_valid(base) == -1) return; diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 59a384a..47d595c 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -10,10 +10,6 @@ #include <device/azalia_device.h> #include "pch.h"
-#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -48,15 +44,15 @@ u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) goto no_codec;
/* Write back the value once reset bit is set. */ - write16(base + 0x0, - read16(base + 0x0)); + write16(base + HDA_GCAP_REG, + read16(base + HDA_GCAP_REG));
/* Read in Codec location (BAR + 0xe)[2..0]*/ - reg8 = read8(base + 0xe); + reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f; if (!reg8) goto no_codec; @@ -66,7 +62,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } @@ -155,14 +151,14 @@ }
reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32);
if (wait_for_valid(base) == -1) { printk(BIOS_DEBUG, " codec not valid.\n"); return; }
- reg32 = read32(base + 0x64); + reg32 = read32(base + HDA_IR_REG);
/* 2 */ printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); @@ -179,7 +175,7 @@ if (wait_for_ready(base) == -1) return;
- write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]);
if (wait_for_valid(base) == -1) return; @@ -199,7 +195,7 @@ if (wait_for_ready(base) == -1) return;
- write32(base + 0x60, pc_beep_verbs[i]); + write32(base + HDA_IC_REG, pc_beep_verbs[i]);
if (wait_for_valid(base) == -1) return; @@ -268,9 +264,9 @@ /* Codec Initialization Programming Sequence */
/* Take controller out of reset */ - reg32 = read32(base + 0x08); - reg32 |= (1 << 0); - write32(base + 0x08, reg32); + reg32 = read32(base + HDA_GCTL_REG); + reg32 |= HDA_GCTL_CRST; + write32(base + HDA_GCTL_REG, reg32); /* Wait 1ms */ udelay(1000);
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h index 483cd4c..d0f01a2 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.h +++ b/src/southbridge/intel/lynxpoint/hda_verb.h @@ -3,15 +3,8 @@ #ifndef LYNXPOINT_HDA_VERB_H #define LYNXPOINT_HDA_VERB_H
-#define HDA_GCAP_REG 0x00 -#define HDA_GCTL_REG 0x08 -#define HDA_GCTL_CRST (1 << 0) -#define HDA_STATESTS_REG 0x0e -#define HDA_IC_REG 0x60 -#define HDA_IR_REG 0x64 -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) +#include <stdint.h> +#include <device/azalia_device.h>
int hda_codec_detect(u8 *base); int hda_codec_write(u8 *base, u32 size, const u32 *data);