[coreboot-gerrit] Change in ...coreboot[master]: cpu/intel/gen1/smmrelocate: Blacklist false SMRR advertisement

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30710

Change subject: cpu/intel/gen1/smmrelocate: Blacklist false SMRR advertisement
......................................................................

cpu/intel/gen1/smmrelocate: Blacklist false SMRR advertisement

My pineview atom D400 on my Foxconn D41S advertisted SMRR support on
MTRR_CAP_MSR but hangs on writing SMRR. The Intel® 64 and IA-32
Architectures Software Developer’s Manual makes no references to SMRR
in the section "MSRS IN THE 45 NM AND 32 NM INTEL ® ATOM TM PROCESSOR
FAMILY" so it is safe to assume it really isn't supported.

Change-Id: Iee3cdfc21a7ab74b1f83680f43ceb7d6a6089fa3
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/smm/gen1/smmrelocate.c
1 file changed, 21 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30710/1

diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 46f6f93..8bcad54 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -87,6 +87,23 @@
    }
 }

+/* Some CPU's seem to falsely advertise SMRR support in MTRR_CAP_MSR */
+static bool cpu_smrr_blacklisted(void)
+{
+	struct cpuinfo_x86 c;
+	get_fms(&c, cpuid_eax(1));
+	/*
+	 * The Intel® 64 and IA-32 Architectures Software Developer’s Manual
+	 * makes no references to SMRR in the section "MSRS IN THE 45 NM AND
+	 * 32 NM INTEL ® ATOM TM PROCESSOR FAMILY" so it is safe to assume it
+	 * really isn't supported.
+	 */
+	if (c.x86 == 6 && c.x86_model == 0x1c)
+		return true;
+
+	return false;
+}
+
 /* The relocation work is actually performed in SMM context, but the code
  * resides in the ramstage module. This occurs by trampolining from the default
  * SMRAM entry point to here. */
@@ -135,7 +152,7 @@

/* Write SMRR MSRs based on indicated support. */
    mtrr_cap = rdmsr(MTRR_CAP_MSR);
-	if (mtrr_cap.lo & SMRR_SUPPORTED)
+	if (mtrr_cap.lo & SMRR_SUPPORTED && !cpu_smrr_blacklisted())
    	write_smrr(relo_params);

southbridge_clear_smi_status();
@@ -152,6 +169,9 @@
       configuration value instead. */
    const u32 tseg_size = northbridge_get_tseg_size();

+	printk(BIOS_DEBUG, "SMM Relocate: TSEG_BASE: 0x%08x, TSEG_SIZE: 0x%08x\n",
+	       tsegmb, tseg_size);
+
    params->smram_base = tsegmb;
    params->smram_size = tseg_size;
    if (CONFIG_IED_REGION_SIZE != 0) {