cedarhouse1@comcast.net has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38819 )
Change subject: src/cpu/x86: Adjust STM smm_save_state_size ......................................................................
src/cpu/x86: Adjust STM smm_save_state_size
Initial testing of STM support revealed a sizing issue for greater than 4 threads.
This patch reduces the STM smm_save_state_size, which should allow for 24 threads.
Signed-off-by: Eugene D. Myers edmyers@tycho.nsa.gov Change-Id: I025694185469577e072a92ea75cbbb53c24b2c24 --- M src/cpu/x86/mp_init.c 1 file changed, 1 insertion(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/38819/1
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index c747207..5169861 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1046,19 +1046,7 @@ */ if (CONFIG(STM)) { state->smm_save_state_size += - sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); - - /* Currently, the CPU SMM save state size is based on a simplistic - * algorithm. (align on 4K) - * note: In the future, this will need to handle newer x86 processors - * that require alignment of the save state on 32K boundaries. - * The alignment is done here because coreboot has a hard coded - * value of 0x400 for this value. - * Also, this alignment only works on CPUs less than 5 threads - */ - if (CONFIG(STM)) - state->smm_save_state_size = - ALIGN_UP(state->smm_save_state_size, 0x1000); + ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), 0x100); }
/*