[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/pantherlake: Refactor FSP log level control

[Kapil Porwal (Code Review)]

Attention is currently required from: Subrata Banik.

Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85934?usp=email )

The change is no longer submittable: All-Comments-Resolved is unsatisfied now.

Change subject: soc/intel/pantherlake: Refactor FSP log level control
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Patch Set 2:

(1 comment)

File src/soc/intel/pantherlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/85934/comment/b40650be_6b887906?usp... :
PS2, Line 313: 	if (is_enabled) {
             : 		enum fsp_log_level log_level = fsp_map_console_log_level();
             : 		fsp_set_debug_level(m_cfg, log_level, log_level);
             : 	} else {
             : 		/* Disable Serial/MRC debug message */
             : 		fsp_set_debug_level(m_cfg, 0, 0);
             : 	}
```suggestion
    enum fsp_log_level log_level = is_enabled ? fsp_map_console_log_level() : FSP_LOG_LEVEL_DISABLE;
    fsp_set_debug_level(m_cfg, log_level, log_level);
```