[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Disable VT-d for early silicons

[Tim Wawrzynczak (Code Review)]

Attention is currently required from:  Felix Singer, Abhijeet Rao, Maulik V Vaghela, Meera Ravindranath, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59191 )

Change subject: soc/intel/alderlake: Disable VT-d for early silicons
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Patch Set 3: -Code-Review

(1 comment)

File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/59191/comment/78e26db8_eab7ffa8 
PS3, Line 264: cpu_get_cpuid() == CPUID_ALDERLAKE_A0 || CPUID_ALDERLAKE_A1
> So if the first part is false, then this is always true since everything greater than 0 is evaluated […]

Ooph my eyes are broken today, thanks Felix 😄

suggestion:
```
const uint32_t cpuid = cpu_get_cpuid();
if (cpuid == CPUID_ALDERLAKE_A0 || cpuid == CPUID_ALDERLAKE_A1)
```