Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44497
to look at the new patch set (#8).
Change subject: soc/intel/common/block: Add emmc dll tuning ......................................................................
soc/intel/common/block: Add emmc dll tuning
For 3 different operations (CMD, Tx Data, Rx Data) use mmc driver in coreboot to switch speed modes (DS, HS, DDR, HS200, HS400). 1) For each speed mode / operation combination, start writing delay values (each step 125pSec delay) from 0 to max for the corresponding register field. As an example, register "Tx Delay Control 1" 0x824h, bit field [8:14] is for HS400 speed and write operation (Tx Data). Max is 78 for this field. 2) After writing a delay value to the register field, try to send a CMD13 “send status” for CMD operation. For write (Tx Data), send CMD24 "Write Block”. For read (Rx Data), send CMD17 "Read Single Block". 3) Mark that delay value as FAIL if there are crc errors, timeouts, bits set in Error Interrupt Status register or read/write failures. PASS if there are no errors. 4) Choose the middle of largest passing window and program register field with this optimal delay value.
BUG=b:140124451 TEST=Ran tuning on Waddledee and booted to OS via emmc.
Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/soc/intel/common/block/include/intelblocks/mmc.h M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/dll_tuning.c 3 files changed, 383 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/44497/8