Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17534
-gerrit
commit 8f49c9887016a1640ab9ab81ae34e04074a3c74b Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sun Nov 20 11:03:13 2016 +0200
AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT
Vendorcode always does PCI MMCONF access once it is enabled via MSR.
In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores.
Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/cpu/amd/pi/00630F01/Kconfig | 1 + src/cpu/amd/pi/00660F01/Kconfig | 1 + src/cpu/amd/pi/00670F00/Kconfig | 1 + src/cpu/amd/pi/00730F01/Kconfig | 1 + src/mainboard/amd/bettong/romstage.c | 1 + src/mainboard/amd/db-ft3b-lc/romstage.c | 5 +++-- src/mainboard/amd/lamar/romstage.c | 4 +++- src/mainboard/amd/olivehillplus/romstage.c | 5 +++-- src/mainboard/bap/ode_e21XX/romstage.c | 5 +++-- src/northbridge/amd/pi/00630F01/Kconfig | 1 - src/northbridge/amd/pi/00660F01/Kconfig | 1 - src/northbridge/amd/pi/00670F00/Kconfig | 1 - src/northbridge/amd/pi/00730F01/Kconfig | 1 - 13 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index 962b829..5b61a82 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_PI_00630F01 bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00630F01 diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index de74d3c..a556ecc 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_PI_00660F01 bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00660F01 diff --git a/src/cpu/amd/pi/00670F00/Kconfig b/src/cpu/amd/pi/00670F00/Kconfig index d5e3abb..132d7e8 100644 --- a/src/cpu/amd/pi/00670F00/Kconfig +++ b/src/cpu/amd/pi/00670F00/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_PI_00670F00 bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00670F00 diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index cfc5b75..baf7549 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_PI_00730F01 bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00730F01 diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index c3e2aa4..6b12afc 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -32,6 +32,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void *resume_backup_memory; #endif
+ /* Must come first to enable PCI MMCONF. */ amd_initmmio();
hudson_lpc_port80(); diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 5c7796f..79cc0f9 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -37,6 +37,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val;
+ /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been @@ -48,8 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- amd_initmmio(); - hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index f084582..58c6e42 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -41,6 +41,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val;
+ /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been @@ -52,7 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- amd_initmmio(); hudson_lpc_decode();
outb(0x24, 0xCD6); diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 6d1e4ea..534a8e5 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -37,6 +37,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val;
+ /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been @@ -48,8 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- amd_initmmio(); - hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index e45464e..5deeaa8 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -41,6 +41,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val;
+ /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been @@ -52,8 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- amd_initmmio(); - hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig index 293b12d..3669826 100644 --- a/src/northbridge/amd/pi/00630F01/Kconfig +++ b/src/northbridge/amd/pi/00630F01/Kconfig @@ -14,7 +14,6 @@ ## config NORTHBRIDGE_AMD_PI_00630F01 bool - select MMCONF_SUPPORT
if NORTHBRIDGE_AMD_PI_00630F01
diff --git a/src/northbridge/amd/pi/00660F01/Kconfig b/src/northbridge/amd/pi/00660F01/Kconfig index f5d234d..fdae80f 100644 --- a/src/northbridge/amd/pi/00660F01/Kconfig +++ b/src/northbridge/amd/pi/00660F01/Kconfig @@ -14,7 +14,6 @@ ## config NORTHBRIDGE_AMD_PI_00660F01 bool - select MMCONF_SUPPORT
if NORTHBRIDGE_AMD_PI_00660F01
diff --git a/src/northbridge/amd/pi/00670F00/Kconfig b/src/northbridge/amd/pi/00670F00/Kconfig index e349635..a92658a 100644 --- a/src/northbridge/amd/pi/00670F00/Kconfig +++ b/src/northbridge/amd/pi/00670F00/Kconfig @@ -14,7 +14,6 @@ ## config NORTHBRIDGE_AMD_PI_00670F00 bool - select MMCONF_SUPPORT
if NORTHBRIDGE_AMD_PI_00670F00
diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index b8dcd99..47c2323 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -15,7 +15,6 @@ ## config NORTHBRIDGE_AMD_PI_00730F01 bool - select MMCONF_SUPPORT
if NORTHBRIDGE_AMD_PI_00730F01