[coreboot-gerrit] Change in coreboot[master]: sec/intel/txt: Bail if var MTRRs cannot snugly cache the BIOS ACM

[Christian Walter (Code Review)]

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46422 )

Change subject: sec/intel/txt: Bail if var MTRRs cannot snugly cache the BIOS ACM
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Patch Set 1: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/46422/1/src/security/intel/txt/comm... 
File src/security/intel/txt/common.c:

https://review.coreboot.org/c/coreboot/+/46422/1/src/security/intel/txt/comm... 
PS1, Line 273: 	 * do so will cause a TXT reset with Class Code 5, Major Error Code 2.
No minor? Can you add the chipset generation you used as these error codes tend to change between the chipset generations.