Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35849 )
Change subject: src/superio/nuvoton/nct5104d: assign IO port range to control GPIO ......................................................................
src/superio/nuvoton/nct5104d: assign IO port range to control GPIO
SuperIO GPIOs can be also controled directly through access to I/O register, now.
Change-Id: I4ce99bb44e6f5db684170f4190bdc38a944849f6 Signed-off-by: Piotr Kleinschmidt piotr.kleins@gmail.com --- M src/mainboard/pcengines/apu1/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/superio/nuvoton/nct5104d/chip.h M src/superio/nuvoton/nct5104d/superio.c 7 files changed, 84 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/35849/1
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 2e8b8f4..ffbaa69 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -43,6 +43,7 @@ device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d register "irq_trigger_type" = "0" + register "enable_wdt1" = "0" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 @@ -62,7 +63,9 @@ io 0x60 = 0x2e8 irq 0x70 = 3 end - device pnp 2e.8 off end + device pnp 2e.8 on + io 0x60 = 0x220 + end device pnp 2e.f off end # GPIO0 and GPIO1 are conditionally turned on device pnp 2e.007 off end diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 6728228..0fff2f8 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -45,6 +45,7 @@ device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "enable_wdt1" = "0" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 @@ -64,7 +65,9 @@ io 0x60 = 0x2e8 irq 0x70 = 3 end - device pnp 2e.8 off end + device pnp 2e.8 on + io 0x60 = 0x220 + end device pnp 2e.f off end # GPIO0 and GPIO1 are conditionally turned on device pnp 2e.007 on end diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 0c0c21e..bb45fdc 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -45,6 +45,7 @@ device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "enable_wdt1" = "0" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 @@ -64,7 +65,9 @@ io 0x60 = 0x2e8 irq 0x70 = 3 end - device pnp 2e.8 off end + device pnp 2e.8 on + io 0x60 = 0x220 + end device pnp 2e.f off end # GPIO0 and GPIO1 are conditionally turned on device pnp 2e.007 on end diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index c93c04f..1947ce7 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -45,6 +45,7 @@ device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "enable_wdt1" = "0" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 @@ -64,7 +65,9 @@ io 0x60 = 0x2e8 irq 0x70 = 3 end - device pnp 2e.8 off end + device pnp 2e.8 on + io 0x60 = 0x220 + end device pnp 2e.f off end # GPIO0 and GPIO1 are conditionally turned on device pnp 2e.007 on end diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index b6b22cf..4afe265 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -45,6 +45,7 @@ device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "enable_wdt1" = "0" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 @@ -64,7 +65,9 @@ io 0x60 = 0x2e8 irq 0x70 = 3 end - device pnp 2e.8 off end + device pnp 2e.8 on + io 0x60 = 0x220 + end device pnp 2e.f off end device pnp 2e.007 off end device pnp 2e.107 off end diff --git a/src/superio/nuvoton/nct5104d/chip.h b/src/superio/nuvoton/nct5104d/chip.h index d351053..9083dab 100644 --- a/src/superio/nuvoton/nct5104d/chip.h +++ b/src/superio/nuvoton/nct5104d/chip.h @@ -19,6 +19,7 @@
struct superio_nuvoton_nct5104d_config { u8 irq_trigger_type; + u8 enable_wdt1; };
#endif diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 40d1200..9e5f754 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -15,10 +15,12 @@ */
#include <device/pnp.h> +#include <device/device.h> #include <superio/conf_mode.h> #include <stdlib.h> #include "nct5104d.h" #include "chip.h" +#include "console/console.h"
static void set_irq_trigger_type(struct device *dev, bool trig_level) { @@ -106,6 +108,63 @@ pnp_write_config(dev, 0x1c, reg); }
+static void enable_gpio_io_port(struct device *dev, u8 enable_wdt1) +{ + u8 reg; + u16 io_base_address; + u8 uartc_enabled, uartd_enabled; + u8 sio_port; + + sio_port = dev->path.pnp.port; + + pnp_write_config(dev, 0x07, NCT5104D_GPIO_WDT); + + /* Devictree always sets LDN 8 CR30.0 bit (WDT1 enable) + * See if user really wants Watchdog Timer 1 to be enabled + */ + + if(enable_wdt1 != 0) { + reg = pnp_read_config(dev, 0x30); + pnp_write_config(dev, 0x30, reg & 0xFE); + } + + /* Check if UARTC and UARTD are both enabled + * If they are, don't activate GPIO Address Mode + * In any other case - activate GPIO Address Mode + */ + + struct device *uart; + + uart = dev_find_slot_pnp(sio_port, NCT5104D_SP3); + uartc_enabled = uart->enabled; + + uart = dev_find_slot_pnp(sio_port, NCT5104D_SP4); + uartd_enabled = uart->enabled; + + if (!uartc_enabled || !uartd_enabled) { + + /* Check if LDN 8 CR60 and CR61 contain valid IO Base Address + * IO Base Address <100h ; FF8h> + */ + + pnp_write_config(dev, 0x07, NCT5104D_GPIO_WDT); + + io_base_address = pnp_read_config(dev, 0x61); + io_base_address |= (pnp_read_config(dev, 0x60) << 8); + + if (io_base_address < 0x100 || io_base_address > 0xFF8) { + printk(BIOS_ERR, "Invalid io base address %x != " + "<100h ; FF8h> \n", io_base_address); + + return; + } + + /* Set LDN 8 CR 30.1 to activate GPIO Address Mode */ + reg = pnp_read_config(dev, 0x30); + pnp_write_config(dev, 0x30, reg | 0x02); + } +} + static void nct5104d_init(struct device *dev) { struct superio_nuvoton_nct5104d_config *conf = dev->chip_info; @@ -129,6 +188,9 @@ case NCT5104D_GPIO1: route_pins_to_uart(dev, false); break; + case NCT5104D_GPIO_WDT: + enable_gpio_io_port(dev, conf->enable_wdt1); + break; default: break; } @@ -151,7 +213,7 @@ { NULL, NCT5104D_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, { NULL, NCT5104D_SP3, PNP_IO0 | PNP_IRQ0, 0x07f8, }, { NULL, NCT5104D_SP4, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, NCT5104D_GPIO_WDT}, + { NULL, NCT5104D_GPIO_WDT, PNP_IO0, 0x07f8, }, { NULL, NCT5104D_GPIO_PP_OD}, { NULL, NCT5104D_GPIO0}, { NULL, NCT5104D_GPIO1},