[coreboot-gerrit] Change in coreboot[master]: coreboot:[TEST ONLY] Add support for boot with tianocore payload

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35376 )

Change subject: coreboot:[TEST ONLY] Add support for boot with tianocore payload
......................................................................

coreboot:[TEST ONLY] Add support for boot with tianocore payload

Add FSP UPDs and set gbb flags through Kconfig required
to boot with tianocore payload.

Change-Id: I42fcf23523889d47f0490fad662ca6b3587ab548
Signed-off-by: Meera Ravindranath 
---
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/soc/intel/cannonlake/fsp_params.c
3 files changed, 4 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/35376/1

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index c4c9146..259827f 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -21,6 +21,8 @@
    select MAINBOARD_HAS_TPM2
    select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
    select SYSTEM_TYPE_LAPTOP
+	select GBB_FLAG_ENABLE_ALTERNATE_OS
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC

if BOARD_GOOGLE_BASEBOARD_HATCH

diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 7382209..1637765 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -56,7 +56,7 @@
    # putting it under register "common_soc_config" in overridetree.cb file.
    register "common_soc_config.pch_thermal_trip" = "77"

-	register "PmTimerDisabled" = "1"
+	register "PmTimerDisabled" = "0"

# VR Settings Configuration for 4 Domains
    #+----------------+-------+-------+-------+-------+
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index f48a626..dbaedb7 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -249,6 +249,7 @@

/* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
+	params->Enable8254ClockGating = 0;
    params->Enable8254ClockGatingOnS3 = 1;

/* USB */