Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )
Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... PS5, Line 142: set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT);
I wonder how this works. […]
if you could see since SPT (SKL) we are using similar approach. I don't recall about older PCH platform mechanism.
Please refer to https://github.com/coreboot/coreboot/blob/ca38fbcdbfcb5024496d2577f71de06745...
grep -rsn "fast_spi_cache_bios_region" src/
src/soc/intel/skylake/bootblock/cpu.c:23: fast_spi_cache_bios_region(); src/soc/intel/icelake/bootblock/cpu.c:25: fast_spi_cache_bios_region(); src/soc/intel/apollolake/bootblock/bootblock.c:107: fast_spi_cache_bios_region(); src/soc/intel/apollolake/cpu.c:287: fast_spi_cache_bios_region(); src/soc/intel/cannonlake/bootblock/cpu.c:26: fast_spi_cache_bios_region();