Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 )
Change subject: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode ......................................................................
Patch Set 8:
If LPSS (SIO DMA1) pci device 0/30/0 is configured in ACPI mode, PWM, HS2UARTS, and SPI controller needs to be configured in ACPI mode. If LPSS (SIO DMA2) pci device 0/24/0 is configured in ACPI mode, I2C controller needs to be configured in ACPI mode. In other words: If function > 1 in PCI mode, function 0 must be PCI mode to be PCI-enumerated. (See 33.1 of Intel Braswell BIOS Writes Guide) (See 24.3 of Intel Braswell External Design Guide Volume 2)
This is NOT a bug in FSP. I expect it's responsibility of coreboot/developer to provide correct parameters API of FSP.
IMO it is still a BUG in FSP docs. The FSP docs do not document ACPI mode for DMAs and the dependency for child devices following the parent device setting. How a developer can integrate the binary correctly when the documentation and API have bugs? Not everyone has access to FSP source code, let's keep that in mind.