Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35018 )
Change subject: soc/amd/common/block: Create new SPI code ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35018/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35018/2//COMMIT_MSG@10 PS2, Line 10: controller within the FCH to its fullest.
What is currently not supported?
Write protection using SPI controller functionality is not supported using current SPI code, but is supported by this patch. Consequently currently SPI write protection works only with some SPI that do implement it using SPI in chip write protection.
https://review.coreboot.org/c/coreboot/+/35018/2//COMMIT_MSG@11 PS2, Line 11:
Please add the datasheet name and revision.
Only datasheet used were Family 15h BKDG revision 3.06 (public) and Family 17h (NDA). The SPI controller is identical in both, except for the size of the FIFO (which is declared in SOC specific southbridge.h). I'll add only the Family 15h which is already public.
https://review.coreboot.org/c/coreboot/+/35018/2/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/35018/2/src/soc/amd/common/block/sp... PS2, Line 5: Select this option to add SPI controller functions to the build.
Can you be more specific? Without it generic SPI controller functions would be used, or none at all?
From what I understood on Martin's request, the idea is to eventually abandon device/spi/spi_flash.c as much as possible, as Intel currently overrides it with fast_spi. He asked me to specifically override flash_ops structure, just as fast_spi does. So yes, I could be more specific, but when config SPI_FLASH becomes deprecated I would need to remove the extra help.