Omar Pakker just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15967
-gerrit
commit 8d8807590358fac9960a7b8bd8259dd7b5e442d2 Author: Omar Pakker omarpakker+coreboot@gmail.com Date: Fri Jul 29 19:05:33 2016 +0200
superio/nuvoton: Add Nuvoton NCT6791D
This adds support for Nuvoton NCT6791D Super I/O chips. Makes use of the common Nuvoton early_serial.c.
Based on the Datasheet supplied by Nuvoton. Datasheet Version: January 8th, 2016 Revision 1.11
Change-Id: I027d33b85f0dc6ee50deebdccaecc74487eecb40 Signed-off-by: Omar Pakker omarpakker+coreboot@gmail.com --- src/superio/nuvoton/Kconfig | 4 ++ src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/nct6791d/Makefile.inc | 16 +++++ src/superio/nuvoton/nct6791d/nct6791d.h | 58 +++++++++++++++++ src/superio/nuvoton/nct6791d/superio.c | 102 ++++++++++++++++++++++++++++++ 5 files changed, 181 insertions(+)
diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig index ce7db26..4067a41 100644 --- a/src/superio/nuvoton/Kconfig +++ b/src/superio/nuvoton/Kconfig @@ -32,3 +32,7 @@ config SUPERIO_NUVOTON_NCT5572D config SUPERIO_NUVOTON_NCT6779D bool select SUPERIO_NUVOTON_COMMON_ROMSTAGE + +config SUPERIO_NUVOTON_NCT6791D + bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index eb3dd5d..94cc6b7 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -20,3 +20,4 @@ subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d diff --git a/src/superio/nuvoton/nct6791d/Makefile.inc b/src/superio/nuvoton/nct6791d/Makefile.inc new file mode 100644 index 0000000..db5c620 --- /dev/null +++ b/src/superio/nuvoton/nct6791d/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Omar Pakker omarpakker+coreboot@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += superio.c diff --git a/src/superio/nuvoton/nct6791d/nct6791d.h b/src/superio/nuvoton/nct6791d/nct6791d.h new file mode 100644 index 0000000..69855ac --- /dev/null +++ b/src/superio/nuvoton/nct6791d/nct6791d.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Omar Pakker omarpakker+coreboot@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_NUVOTON_NCT6791D_H +#define SUPERIO_NUVOTON_NCT6791D_H + +/* Logical Device Numbers (LDN). */ +#define NCT6791D_PP 0x01 /* Parallel port */ +#define NCT6791D_SP1 0x02 /* UART A */ +#define NCT6791D_SP2 0x03 /* UART B, IR */ +#define NCT6791D_KBC 0x05 /* Keyboard Controller */ +#define NCT6791D_CIR 0x06 /* Consumer IR */ +#define NCT6791D_GPIO678 0x07 /* GPIO 6, 7 & 8 */ +#define NCT6791D_WDT1_WDTMEM_GPIO01 0x08 /* WDT1, WDT_MEM, GPIO 0 & 1 */ +#define NCT6791D_GPIO2345 0x09 /* GPIO 2, 3, 4 & 5 */ +#define NCT6791D_ACPI 0x0A /* ACPI */ +#define NCT6791D_HWM_FPLED 0x0B /* HW Monitor, Front Panel LED */ +#define NCT6791D_BCLK_WDT2_WDTMEM 0x0D /* BCLK, WDT2, WDT_MEM */ +#define NCT6791D_CIRWUP 0x0E /* CIR Wake-Up */ +#define NCT6791D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open-Drain */ +#define NCT6791D_PORT80 0x14 /* Port 80 UART */ +#define NCT6791D_DS 0x16 /* Deep Sleep */ + +/* Virtual LDNs */ +#define NCT6791D_WDT1 ((0 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01) +#define NCT6791D_WDTMEM ((4 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01) +#define NCT6791D_GPIOBASE ((3 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01) +#define NCT6791D_GPIO0 ((1 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01) +#define NCT6791D_GPIO1 ((7 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01) +#define NCT6791D_GPIO2 ((0 << 8) | NCT6791D_GPIO2345) +#define NCT6791D_GPIO3 ((1 << 8) | NCT6791D_GPIO2345) +#define NCT6791D_GPIO4 ((2 << 8) | NCT6791D_GPIO2345) +#define NCT6791D_GPIO5 ((3 << 8) | NCT6791D_GPIO2345) +#define NCT6791D_GPIO6 ((0 << 8) | NCT6791D_GPIO678) +#define NCT6791D_GPIO7 ((1 << 8) | NCT6791D_GPIO678) +#define NCT6791D_GPIO8 ((2 << 8) | NCT6791D_GPIO678) +#define NCT6791D_DS5 ((0 << 8) | NCT6791D_DS) +#define NCT6791D_DS3 ((1 << 8) | NCT6791D_DS) +#define NCT6791D_PCHDSW ((3 << 8) | NCT6791D_DS) +#define NCT6791D_DSWWOPT ((4 << 8) | NCT6791D_DS) +#define NCT6791D_DS3OPT ((5 << 8) | NCT6791D_DS) +#define NCT6791D_DSDSS ((6 << 8) | NCT6791D_DS) +#define NCT6791D_DSPU ((7 << 8) | NCT6791D_DS) + +#endif /* SUPERIO_NUVOTON_NCT6791D_H */ diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c new file mode 100644 index 0000000..0a0f0be --- /dev/null +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held felix-coreboot@felixheld.de + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com + * Copyright (C) 2015 Matt DeVillier matt.devillier@gmail.com + * Copyright (C) 2016 Omar Pakker omarpakker+coreboot@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "nct6791d.h" + + +static void nct6791d_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case NCT6791D_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6791d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, NCT6791D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6791D_SP1, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6791D_SP2, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6791D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, NCT6791D_CIR, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6791D_ACPI}, + { &ops, NCT6791D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + {0x0ffe, 0}, {0x0ffe, 4}, }, + { &ops, NCT6791D_BCLK_WDT2_WDTMEM}, + { &ops, NCT6791D_CIRWUP, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6791D_GPIO_PP_OD}, + { &ops, NCT6791D_PORT80}, + { &ops, NCT6791D_WDT1}, + { &ops, NCT6791D_WDTMEM}, + { &ops, NCT6791D_GPIOBASE, PNP_IO0, + {0x0ff8, 0}, }, + { &ops, NCT6791D_GPIO0}, + { &ops, NCT6791D_GPIO1}, + { &ops, NCT6791D_GPIO2}, + { &ops, NCT6791D_GPIO3}, + { &ops, NCT6791D_GPIO4}, + { &ops, NCT6791D_GPIO5}, + { &ops, NCT6791D_GPIO6}, + { &ops, NCT6791D_GPIO7}, + { &ops, NCT6791D_GPIO8}, + { &ops, NCT6791D_DS5}, + { &ops, NCT6791D_DS3}, + { &ops, NCT6791D_PCHDSW}, + { &ops, NCT6791D_DSWWOPT}, + { &ops, NCT6791D_DS3OPT}, + { &ops, NCT6791D_DSDSS}, + { &ops, NCT6791D_DSPU}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6791d_ops = { + CHIP_NAME("NUVOTON NCT6791D Super I/O") + .enable_dev = enable_dev, +}; +