Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47899 )
Change subject: mb/google/hatch: Drop use of SPD cache for puff-based variants ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47899/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47899/1//COMMIT_MSG@11 PS1, Line 11: it's actually slower than simply letting FSP (vs coreboot) : read the SPD data via smbus, so drop it.
It would also be good to test just removing a DIMM or adding a DIMM (i.e. […]
The original idea is the read speed of SPI rom should faster than reading from smbus and also solving the detection issue when adding or removing SODIMM. It's a risk if the MRC_CACHE won't be update when you change to another DIMM or adding a new DIMM.
https://review.coreboot.org/c/coreboot/+/47899/1//COMMIT_MSG@19 PS1, Line 19: Test: build/boot WYVERN variant, check boot times via cbmem: : w/SPD caching: ~722 ms : w/FSP reading: ~627 ms
This time difference is from platform_fsp_memory_init_params_cb() / mainboard_memory_init_params() a […]
Do a quick check with a puff variant project in my side. There are two SODIMM installed on the device. I saw w/SPD cache faster than using fsp to read spd 19ms when cold reboot, but slower 6ms when warm reboot. Hi Matt, Do you see the different between cold reboot and warm reboot?
With SPD cache 1265891 Cold reboot 1062252 warm reset
With this patch 1284142 Cold reboot 1056183 warm reset