John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41537 )
Change subject: soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method ......................................................................
soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method
CPU to PCH method refers to PCH ACPI operation region which was wrongly defined as SystemMemory and PCH_PWRM_BASE_ADDRESS. Change the operation region to be SystemIO and ACPI_BASE_ADDRESS.
BUG=b:156530805 TEST=Built and booted to kernel.
Signed-off-by: John zhao john.zhao@intel.com Change-Id: Ifa291a993ec23e1e4dfad8f6cdfabc80b824d20c --- M src/soc/intel/tigerlake/acpi/tcss.asl 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/41537/1
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 7d586dd..abdcb51 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -45,10 +45,10 @@ }
/* - * Define PCH ACPIBASE as an ACPI operating region. The base address can be + * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be * found in Device 31, Function 2, Offset 40h. */ - OperationRegion (PMIO, SystemMemory, PCH_PWRM_BASE_ADDRESS, 0x80) + OperationRegion (PMIO, SystemIO, ACPI_BASE_ADDRESS, 0x80) Field (PMIO, ByteAcc, NoLock, Preserve) { Offset(0x6C), /* 0x6C, General Purpose Event 0 Status [127:96] */ , 19,