Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38490 )
Change subject: soc/mediatek/mt8183: improve the DRAMC runtime config flow ......................................................................
Patch Set 1:
(8 comments)
https://review.coreboot.org/c/coreboot/+/38490/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38490/1//COMMIT_MSG@9 PS1, Line 9: move Move
https://review.coreboot.org/c/coreboot/+/38490/1//COMMIT_MSG@10 PS1, Line 10: BRANCH=kukui BUG=? TEST=?
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... PS1, Line 290: (0x7 << 28) | (0x7 << 24), (0x1 << 28) | (0x0 << 24)); Align with previous line.
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... PS1, Line 323: size_t Couldn't this be u8 (for consistency)?
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... PS1, Line 326: (0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21)); Align with previous line.
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... PS1, Line 361: write32(&ch[chn].phy.ca_dll_fine_tune[3], 0x3a000); write32(&ch[chn].phy.ca_dll_fine_tune[3], chn == CHANNEL_A ? 0xba000 : 0x3a000);
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... PS1, Line 381: setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20); Is this bug fix or improvement?
https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... PS1, Line 431: /* RX_TRACKING: ON */ Wrong indent.