Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34805 )
Change subject: arch/x86: Add postcar_frame_setup_top_of_dram_usage() API ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34805/2/src/arch/x86/postcar_loader... File src/arch/x86/postcar_loader.c:
https://review.coreboot.org/c/coreboot/+/34805/2/src/arch/x86/postcar_loader... PS2, Line 135: MTRR_TYPE_WRPROT
yes, i will come up with more debug data, right now my observation says, if i make it WB and the mom […]
After talking to cache architect, i'm getting confirmation about NEM mode
here is problem statement why we have introduced NEM enhance mode:
Google Chromebook BIOS doesn’t fit the provided LLC size (can be as small as 1.5M for the product with 2 cores and 1M LLC ) Their request: Code size (RO): up to 16M Data size (RW): up to 256K
Idea: If we could make sure that data always remains in cache while code line are get replaced – we could allow unlimited code size along with the well defined limited data size
New request: now we are asking to expand data size with newly DRAM range (top of DRAM) and cache this region as well in another MTRR with WB
Yes, I think it’s not supposed to work. MTRR’s for NEM mode should be set up before enabling the NEM mode via MSR. You cannot add another WB region (DRAM) while already in NEM mode.
interestingly marking this area WB vs WP, i don't see much savings in boot time. Its ~1-1.5ms delta between two