[coreboot-gerrit] Change in coreboot[master]: src/arch/arm/include/armv7/arch/cache.h:

[Athanasios Kastoras (Code Review)]

Athanasios Kastoras has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63125 )

Change subject: src/arch/arm/include/armv7/arch/cache.h:
......................................................................

src/arch/arm/include/armv7/arch/cache.h:

Remove unnecessary whitespace before closing parenthesis at inline assembly statements
on lines 237 and 252

Signed-off-by: Thanos Kastoras 
Change-Id: I7aa8174837ff7d20a8217d75e2028a62a381aede
---
M src/arch/arm/include/armv7/arch/cache.h
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/63125/1

diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
index e332c31..6054fed 100644
--- a/src/arch/arm/include/armv7/arch/cache.h
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -234,7 +234,7 @@
     * Note: L2CTLR can only be written when the L2 memory system
     * is idle, ie before the MMU is enabled.
     */
-	asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" );
+	asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
    isb();
 }

@@ -249,7 +249,7 @@
 /* write L2 Auxiliary Control Register (L2ACTLR) */
 static inline void write_l2actlr(uint32_t val)
 {
-	asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" );
+	asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory");
    isb();
 }