Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82673?usp=email )
(
26 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/novacustom: add V5x0TU board (Meteor Lake) ......................................................................
mb/novacustom: add V5x0TU board (Meteor Lake)
NovaCustom (Clevo) V5x0TU are two laptops with Intel Core Ultra (Meteor Lake) series processors.
Two variants (V540TU and V560TU) are supported. Their EC firmware is different due to keyboard layout changes. On coreboot's side, the only difference are SMBIOS strings.
Working: - DDR5 SODIMM in slot RAM2 - M.2 2280 PCIe slots - Thunderbolt, USB ports - Video outputs in OS and firmware via FSP GOP - I2C touchpad, webcam, SD Card reader - S0ix - Booting Ubuntu 24.04 with edk2 UefiPayload - Vboot, TPM measured boot
VBT was extracted from Clevo Insyde firmware, version v1.07.2.
Change-Id: I82c73ddb1e76a9baf9b97e13124aa249ae1c2771 Signed-off-by: Michał Kopeć michal.kopec@3mdeb.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/82673 Reviewed-by: Krystian Hebel krystian.hebel@3mdeb.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/mainboard/novacustom/Kconfig A src/mainboard/novacustom/Kconfig.name A src/mainboard/novacustom/mtl-h/Kconfig A src/mainboard/novacustom/mtl-h/Kconfig.name A src/mainboard/novacustom/mtl-h/Makefile.mk A src/mainboard/novacustom/mtl-h/acpi/backlight.asl A src/mainboard/novacustom/mtl-h/acpi/mainboard.asl A src/mainboard/novacustom/mtl-h/board_info.txt A src/mainboard/novacustom/mtl-h/bootblock.c A src/mainboard/novacustom/mtl-h/cmos.default A src/mainboard/novacustom/mtl-h/cmos.layout A src/mainboard/novacustom/mtl-h/data.vbt A src/mainboard/novacustom/mtl-h/devicetree.cb A src/mainboard/novacustom/mtl-h/dsdt.asl A src/mainboard/novacustom/mtl-h/fadt.c A src/mainboard/novacustom/mtl-h/gpio.c A src/mainboard/novacustom/mtl-h/gpio_early.c A src/mainboard/novacustom/mtl-h/hda_verb.c A src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h A src/mainboard/novacustom/mtl-h/ramstage.c A src/mainboard/novacustom/mtl-h/romstage.c A src/mainboard/novacustom/mtl-h/vboot-rwab.fmd 22 files changed, 1,383 insertions(+), 0 deletions(-)
Approvals: Krystian Hebel: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/novacustom/Kconfig b/src/mainboard/novacustom/Kconfig new file mode 100644 index 0000000..e159480 --- /dev/null +++ b/src/mainboard/novacustom/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_NOVACUSTOM + +choice + prompt "Mainboard model" + +source "src/mainboard/novacustom/*/Kconfig.name" + +endchoice + +source "src/mainboard/novacustom/*/Kconfig" + +config MAINBOARD_VENDOR + default "NovaCustom" + +endif # VENDOR_NOVACUSTOM diff --git a/src/mainboard/novacustom/Kconfig.name b/src/mainboard/novacustom/Kconfig.name new file mode 100644 index 0000000..242b3bb --- /dev/null +++ b/src/mainboard/novacustom/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_NOVACUSTOM + bool "NovaCustom" diff --git a/src/mainboard/novacustom/mtl-h/Kconfig b/src/mainboard/novacustom/mtl-h/Kconfig new file mode 100644 index 0000000..5d608b4 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Kconfig @@ -0,0 +1,105 @@ +config BOARD_NOVACUSTOM_MTLH_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GFX_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select DRIVERS_WIFI_GENERIC + select EC_DASHARO_EC + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select NO_UART_ON_SUPERIO + select PMC_IPC_ACPI_INTERFACE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_CRASHLOG + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_METEORLAKE_U_H + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config BOARD_NOVACUSTOM_V5X0TU_BASE + bool + select BOARD_NOVACUSTOM_MTLH_COMMON + select MAINBOARD_USES_IFD_GBE_REGION + +config BOARD_NOVACUSTOM_V540TU + bool + select BOARD_NOVACUSTOM_V5X0TU_BASE + +config BOARD_NOVACUSTOM_V560TU + bool + select BOARD_NOVACUSTOM_V5X0TU_BASE + +if BOARD_NOVACUSTOM_MTLH_COMMON + +config MAINBOARD_DIR + default "novacustom/mtl-h" + +config MAINBOARD_PART_NUMBER + default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE + +config MAINBOARD_SMBIOS_MANUFACTURER + default "Notebook" + +config MAINBOARD_VERSION + default "V540TU" if BOARD_NOVACUSTOM_V540TU + default "V560TU" if BOARD_NOVACUSTOM_V560TU + +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match Insyde firmware, for Windows Update + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config DIMM_SPD_SIZE + default 1024 + +config POST_DEVICE + default n + +config USE_PM_ACPI_TIMER + default n + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT + +config VBOOT_SLOTS_RW_AB + default y if VBOOT + +config VBOOT_VBNV_OFFSET + default 0x28 + +config TPM_PIRQ + default 0x61 # GPP_E01 + +config FMDFILE + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT && VBOOT_SLOTS_RW_AB + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config EC_DASHARO_EC_FLASH_SIZE + default 0x40000 + +endif diff --git a/src/mainboard/novacustom/mtl-h/Kconfig.name b/src/mainboard/novacustom/mtl-h/Kconfig.name new file mode 100644 index 0000000..ff079a0 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Kconfig.name @@ -0,0 +1,7 @@ +comment "Meteor Lake H" + +config BOARD_NOVACUSTOM_V540TU + bool "V540TU (14")" + +config BOARD_NOVACUSTOM_V560TU + bool "V560TU (16")" diff --git a/src/mainboard/novacustom/mtl-h/Makefile.mk b/src/mainboard/novacustom/mtl-h/Makefile.mk new file mode 100644 index 0000000..9a35f5a --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Makefile.mk @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + +romstage-y += romstage.c + +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-y += gpio.c + +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/novacustom/mtl-h/acpi/backlight.asl b/src/mainboard/novacustom/mtl-h/acpi/backlight.asl new file mode 100644 index 0000000..01fa83e --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/backlight.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/gma/acpi/gma.asl> + +Scope (GFX0) +{ + Name (BRIG, Package (23) { + 40, /* default AC */ + 40, /* default Battery */ + 0, + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl b/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl new file mode 100644 index 0000000..ec22903 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#include <ec/dasharo/ec/acpi/ec.asl> + +Scope (_SB) { + Scope (PCI0) { + #include "backlight.asl" + } +} diff --git a/src/mainboard/novacustom/mtl-h/board_info.txt b/src/mainboard/novacustom/mtl-h/board_info.txt new file mode 100644 index 0000000..4b3db96 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: NovaCustom +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/novacustom/mtl-h/bootblock.c b/src/mainboard/novacustom/mtl-h/bootblock.c new file mode 100644 index 0000000..8d06adc --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <mainboard/gpio.h> + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/novacustom/mtl-h/cmos.default b/src/mainboard/novacustom/mtl-h/cmos.default new file mode 100644 index 0000000..62715bc --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +me_state=Enable diff --git a/src/mainboard/novacustom/mtl-h/cmos.layout b/src/mainboard/novacustom/mtl-h/cmos.layout new file mode 100644 index 0000000..66b8665 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/cmos.layout @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 304 r 0 reserved_memory + +# coreboot config options: ramtop +304 80 h 0 ramtop + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter + +# Vboot non-volatile data +432 128 r 0 vbnv + +984 16 h 0 check_sum + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 431 984 diff --git a/src/mainboard/novacustom/mtl-h/data.vbt b/src/mainboard/novacustom/mtl-h/data.vbt new file mode 100644 index 0000000..59c3c78 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/data.vbt Binary files differ diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb new file mode 100644 index 0000000..663d694 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/devicetree.cb @@ -0,0 +1,316 @@ +chip soc/intel/meteorlake + # Common SoC configuration + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable S0ix / Modern Standby + register "s0ix_enable" = "1" + + # SaGv configuration + register "sagv" = "SAGV_ENABLED" + + # Disable C1 and Package C-state auto-demotion + register "disable_c1_state_auto_demotion" = "1" + register "disable_package_c_state_demotion" = "1" + + # Enable Energy Reporting + register "pch_pm_energy_report_enable" = "1" + + # Thermal + register "tcc_offset" = "10" # TCC of 100C + + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC_SKIP), /* USB Type-A Port 1 (Left) */ + [1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 1 (Non-TBT) */ + [2] = USB2_PORT_MID(OC_SKIP), /* USB Type-A Port 2 (Right) */ + [5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 2 (TBT) */ + [6] = USB2_PORT_LONG(OC_SKIP), /* Integrated Camera */ + [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth on M.2 2230 */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 1 (Left) */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 2 (Right) */ + }" + + register "tcss_ports" = "{ + [0] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 1 (TBT) */ + [1] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 2 (Non-TBT) */ + }" + + device cpu_cluster 0 on end + device domain 0 on + subsystemid 0x1558 0xa743 inherit + device ref system_agent on end + device ref igpu on + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, /* eDP */ + [DDI_PORT_2] = DDI_ENABLE_DDC | DDI_ENABLE_HPD, /* HDMI 2.1 */ + }" + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB unused + register "device[1].name" = ""DD01"" + # TCP0 for Thunderbolt 4 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))" + # TCP1 unused + register "device[3].name" = ""DD03"" + # TCP2 for HDMI 2.1 + register "device[4].name" = ""DD04"" + # TCP3 unused + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end + device ref dtt on end + device ref pcie_rp10 on # M.2 2280 #2 + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D01)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + register "srcclk_pin" = "8" + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + device ref pcie_rp11 on # M.2 2280 #1 + register "pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 7, + .clk_req = 7, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D05)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)" + register "srcclk_pin" = "7" + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device ref tbt_pcie_rp0 on end + device ref gna on end + device ref crashlog on end + device ref vpu on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 1 (TBT)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + end + device ref ioe_shared_sram on end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Left"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 1 (TBT)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Left"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Right"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))" + device ref usb3_port2 on end + end + end + end + end + device ref pmc_shared_sram on end + device ref cnvi_wifi on + register "cnvi_wifi_core" = "true" + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c0 on # Touchpad + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c1 on # USB-PD EEPROM + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref i2c3 on # Pantone ROM + register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci" + end + device ref pcie_rp5 on # GLAN + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED, + }" + register "pcie_clk_config_flag[2]" = "PCIE_CLK_LAN" + end + device ref pcie_rp6 on # SD Card Reader + register "pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + end + device ref pcie_rp8 on # M.2 2230 + register "pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_09" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device ref uart0 on # BIOS Debug Port + register "serial_io_uart_mode[PchSerialIoIndexUART0]" = "PchSerialIoPci" + end + device ref soc_espi on + register "gen1_dec" = "0x00040069" # EC PM channel + register "gen2_dec" = "0x00fc0e01" # AP/EC command + register "gen3_dec" = "0x00fc0f01" # AP/EC debug + chip drivers/pc80/tpm # SLB 9672 TPM 2.0 + device pnp 0c31.0 on end + end + end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_V" + register "pmc_gpe0_dw1" = "PMC_GPP_B" + register "pmc_gpe0_dw2" = "PMC_GPP_S" + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # USB Type-C Port 1 (TBT) + use usb2_port6 as usb2_port + use tcss_usb3_port0 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + # USB Type-C Port 2 (Non-TBT) + use usb2_port2 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref hda on + subsystemid 0x1558 0xa763 + #register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + + end + device ref smbus on end + device ref fast_spi on end + device ref gbe on end + end +end diff --git a/src/mainboard/novacustom/mtl-h/dsdt.asl b/src/mainboard/novacustom/mtl-h/dsdt.asl new file mode 100644 index 0000000..06e7263 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/dsdt.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/meteorlake/acpi/southbridge.asl> + #include <soc/intel/meteorlake/acpi/tcss.asl> + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (_SB.PCI0.LPCB) + { + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/novacustom/mtl-h/fadt.c b/src/mainboard/novacustom/mtl-h/fadt.c new file mode 100644 index 0000000..f983717 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/fadt.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_MOBILE; +} diff --git a/src/mainboard/novacustom/mtl-h/gpio.c b/src/mainboard/novacustom/mtl-h/gpio.c new file mode 100644 index 0000000..f52b044 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/gpio.c @@ -0,0 +1,574 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group V ------- */ + + /* GPP_V00 - BATLOW# */ + PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1), + /* GPP_V01 - ACPRESENT */ + PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1), + /* GPP_V02 - SOC_WAKE# */ + PAD_CFG_NF(GPP_V02, NATIVE, DEEP, NF1), + /* GPP_V03 - PWRBTN# */ + PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), + /* GPP_V04 - SLP_S3# */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05 - SLP_S4# */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06 - SLP_A# */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V07 - GPIO */ + PAD_CFG_GPO(GPP_V07, 0, DEEP), + /* GPP_V08 - SUSCLK */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09 - SLP_WLAN# */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10 - SLP_S5# */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11 - LANPHYPC */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), + /* GPP_V12 - SLP_LAN# */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V13 - GPIO */ + PAD_CFG_GPO(GPP_V13, 0, DEEP), + /* GPP_V14 - WAKE# */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V15 - GPIO */ + PAD_CFG_GPO(GPP_V15, 0, DEEP), + /* GPP_V16 - GPIO */ + PAD_CFG_GPO(GPP_V16, 0, DEEP), + /* GPP_V17 - GPIO */ + PAD_CFG_GPO(GPP_V17, 0, DEEP), + /* GPP_V18 - GPIO */ + PAD_CFG_GPO(GPP_V18, 0, DEEP), + /* GPP_V19 - n/a */ + PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1), + /* GPP_V20 - n/a */ + PAD_CFG_NF(GPP_V20, NONE, DEEP, NF1), + /* GPP_V21 - n/a */ + PAD_CFG_NF(GPP_V21, NONE, DEEP, NF1), + /* GPP_V22 - GPIO */ + PAD_CFG_GPO(GPP_V22, 0, DEEP), + /* GPP_V23 - GPIO */ + PAD_CFG_GPO(GPP_V23, 0, DEEP), + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C00 - SMBCLK */ + PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1), + /* GPP_C01 - SMBDATA */ + PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1), + /* GPP_C02 - GPIO */ + PAD_CFG_GPO(GPP_C02, 0, DEEP), + /* GPP_C03 - SML0CLK */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), + /* GPP_C04 - SML0DATA */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), + /* GPP_C05 - GPIO */ + PAD_CFG_GPO(GPP_C05, 0, DEEP), + /* GPP_C06 - SML1CLK */ + PAD_CFG_NF(GPP_C06, NONE, RSMRST, NF1), + /* GPP_C07 - SML1DATA */ + PAD_CFG_NF(GPP_C07, NONE, RSMRST, NF1), + /* GPP_C08 - GPIO */ + PAD_CFG_GPO(GPP_C08, 0, DEEP), + /* GPP_C09 - GPIO */ + PAD_CFG_GPO(GPP_C09, 0, DEEP), + /* GPP_C10 - GPIO */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* GPP_C11 - SRCCLKREQ2# */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C12 - SRCCLKREQ3# */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* GPP_C13 - GPIO */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), + /* GPP_C14 - GPIO */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* GPP_C15 - GPIO */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), + /* GPP_C16 - TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17 - TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18 - GPIO */ + PAD_CFG_GPO(GPP_C18, 0, DEEP), + /* GPP_C19 - GPIO */ + PAD_CFG_GPO(GPP_C19, 0, DEEP), + /* GPP_C20 - DDP2_CTRLCLK */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), + /* GPP_C21 - DDP2_CTRLDATA */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), + /* GPP_C22 - GPIO */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* GPP_C23 - GPIO */ + PAD_CFG_GPO(GPP_C23, 0, DEEP), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A00 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), + /* GPP_A01 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), + /* GPP_A02 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), + /* GPP_A03 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), + /* GPP_A04 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), + /* GPP_A05 - ESPI_CLK */ + PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), + /* GPP_A06 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), + /* GPP_A07 - GPIO */ + PAD_CFG_GPO(GPP_A07, 0, DEEP), + /* GPP_A08 - GPIO */ + PAD_CFG_GPO(GPP_A08, 0, DEEP), + /* GPP_A09 - GPIO */ + PAD_CFG_GPO(GPP_A09, 0, DEEP), + /* GPP_A10 - GPIO */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* GPP_A11 - GPIO */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + /* GPP_A12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), + /* GPP_A13 - GPIO */ + PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), + /* GPP_A14 - GPIO */ + PAD_CFG_GPO(GPP_A14, 0, DEEP), + /* GPP_A15 - GPIO */ + PAD_CFG_GPO(GPP_A15, 0, DEEP), + /* GPP_A16 - RSVD */ + PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), + /* GPP_A17 - GPIO */ + PAD_CFG_GPO(GPP_A17, 0, DEEP), + /* GPP_A18 - GPIO */ + PAD_CFG_GPO(GPP_A18, 0, DEEP), + /* GPP_A19 - GPIO */ + PAD_CFG_GPO(GPP_A19, 0, DEEP), + /* GPP_A20 - GPIO */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + /* GPP_A21 - PMCALERT# */ + PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), + /* GPP_A22 - GPIO */ + PAD_NC(GPP_A22, NATIVE), + /* GPP_A23 - GPIO */ + PAD_NC(GPP_A23, NATIVE), + /* GPP_ESPI_CLK_LPBK - n/a */ + PAD_CFG_NF(GPP_ESPI_CLK_LPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E00 - GPIO */ + PAD_CFG_GPO(GPP_E00, 0, DEEP), + /* GPP_E01 - GPIO */ + PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE), + /* GPP_E02 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI), + /* GPP_E03 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI), + /* GPP_E04 - GPIO */ + PAD_CFG_GPO(GPP_E04, 0, DEEP), + /* GPP_E05 - GPIO */ + PAD_CFG_GPO(GPP_E05, 0, DEEP), + /* GPP_E06 - GPIO */ + PAD_CFG_GPO(GPP_E06, 0, DEEP), + /* GPP_E07 - GPIO */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), + /* GPP_E08 - GPIO */ + PAD_CFG_GPO(GPP_E08, 0, DEEP), + /* GPP_E09 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E09, NONE, DEEP, OFF, ACPI), + /* GPP_E10 - GPIO */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), + /* GPP_E11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), + /* GPP_E12 - GPIO */ + PAD_CFG_GPO(GPP_E12, 0, DEEP), + /* GPP_E13 - GPIO */ + PAD_CFG_GPO(GPP_E13, 0, DEEP), + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* GPP_E15 - GPIO */ + PAD_CFG_GPO(GPP_E15, 0, DEEP), + /* GPP_E16 - VRALERT# */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), + /* GPP_E17 - GPIO */ + PAD_CFG_GPO(GPP_E17, 0, DEEP), + /* GPP_E18 - GPIO */ + PAD_CFG_GPO(GPP_E18, 0, DEEP), + /* GPP_E19 - GPIO */ + PAD_CFG_GPO(GPP_E19, 0, DEEP), + /* GPP_E20 - GPIO */ + PAD_CFG_GPO(GPP_E20, 0, DEEP), + /* GPP_E21 - GPIO */ + PAD_CFG_GPO(GPP_E21, 0, DEEP), + /* GPP_E22 - GPIO */ + PAD_CFG_GPO(GPP_E22, 0, DEEP), + /* GPP_E23 - GPIO */ + PAD_NC(GPP_E23, NONE), + /* GPP_THC0_GSPI_CLK_LPBK - GPIO */ + PAD_NC(GPP_THC0_GSPI_CLK_LPBK, NONE), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H00 - GPIO */ + PAD_CFG_GPO(GPP_H00, 0, DEEP), + /* GPP_H01 - GPIO */ + PAD_CFG_GPO(GPP_H01, 0, DEEP), + /* GPP_H02 - GPIO */ + PAD_CFG_GPO(GPP_H02, 0, DEEP), + /* GPP_H03 - GPIO */ + PAD_CFG_GPO(GPP_H03, 0, DEEP), + /* GPP_H04 - GPIO */ + PAD_CFG_GPO(GPP_H04, 0, DEEP), + /* GPP_H05 - GPIO */ + PAD_CFG_GPO(GPP_H05, 0, DEEP), + /* GPP_H06 - I2C3_SDA */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07 - I2C3_SCL */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H08 - GPIO */ + PAD_CFG_GPO(GPP_H08, 0, DEEP), + /* GPP_H09 - GPIO */ + PAD_CFG_GPO(GPP_H09, 0, DEEP), + /* GPP_H10 - GPIO */ + PAD_CFG_GPO(GPP_H10, 0, DEEP), + /* GPP_H11 - GPIO */ + PAD_CFG_GPO(GPP_H11, 0, DEEP), + /* GPP_H12 - GPIO */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + /* GPP_H13 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14 - GPIO */ + PAD_CFG_GPO(GPP_H14, 0, DEEP), + /* GPP_H15 - GPIO */ + PAD_CFG_GPO(GPP_H15, 0, DEEP), + /* GPP_H16 - GPIO */ + PAD_CFG_GPO(GPP_H16, 0, DEEP), + /* GPP_H17 - GPIO */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), + /* GPP_H18 - GPIO */ + PAD_CFG_GPO(GPP_H18, 0, DEEP), + /* GPP_H19 - I2C0_SDA */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H20 - I2C0_SCL */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* GPP_H21 - I2C1_SDA */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22 - I2C1_SCL */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + /* GPP_LPI3C1_CLK_LPBK - GPIO */ + PAD_NC(GPP_LPI3C1_CLK_LPBK, NATIVE), + /* GPP_LPI3C0_CLK_LPBK - n/a */ + PAD_CFG_NF(GPP_LPI3C0_CLK_LPBK, NATIVE, DEEP, NF2), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F00 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), + /* GPP_F02 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), + /* GPP_F04 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05 - MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06 - GPIO */ + PAD_CFG_GPO(GPP_F06, 0, DEEP), + /* GPP_F07 - GPIO */ + PAD_CFG_GPO(GPP_F07, 0, DEEP), + /* GPP_F08 - GPIO */ + PAD_CFG_GPO(GPP_F08, 0, DEEP), + /* GPP_F09 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI), + /* GPP_F10 - GPIO */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + /* GPP_F11 - GPIO */ + PAD_CFG_GPO(GPP_F11, 0, DEEP), + /* GPP_F12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, ACPI), + /* GPP_F13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), + /* GPP_F14 - GPIO */ + PAD_CFG_GPO(GPP_F14, 0, DEEP), + /* GPP_F15 - GPIO */ + PAD_CFG_GPO(GPP_F15, 0, DEEP), + /* GPP_F16 - GPIO */ + PAD_CFG_GPO(GPP_F16, 0, DEEP), + /* GPP_F17 - GPIO */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* GPP_F18 - GPIO */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), + /* GPP_F19 - GPIO */ + PAD_CFG_GPO(GPP_F19, 0, DEEP), + /* GPP_F20 - GPIO */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), + /* GPP_F21 - GPIO */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + /* GPP_F22 - GPIO */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), + /* GPP_F23 - GPIO */ + PAD_CFG_GPO(GPP_F23, 0, DEEP), + /* GPP_THC1_GSPI1_CLK_LPBK - GPIO */ + PAD_NC(GPP_THC1_GSPI1_CLK_LPBK, NONE), + /* GPP_GSPI0A_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_GSPI0A_CLK_LOOPBK, NONE), + + /* ------- GPIO Group SPI ------- */ + + /* ------- GPIO Group VGPIO3 ------- */ + + /* GPP_VGPIO3_USB0 - GPP_VGPIO3_USB0 */ + PAD_CFG_NF(GPP_VGPIO3_USB0, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB1 - GPP_VGPIO3_USB1 */ + PAD_CFG_NF(GPP_VGPIO3_USB1, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB2 - GPP_VGPIO3_USB2 */ + PAD_CFG_NF(GPP_VGPIO3_USB2, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB3 - GPP_VGPIO3_USB3 */ + PAD_CFG_NF(GPP_VGPIO3_USB3, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB4 - GPP_VGPIO3_USB4 */ + PAD_CFG_NF(GPP_VGPIO3_USB4, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB5 - GPP_VGPIO3_USB5 */ + PAD_CFG_NF(GPP_VGPIO3_USB5, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB6 - GPP_VGPIO3_USB6 */ + PAD_CFG_NF(GPP_VGPIO3_USB6, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB7 - GPP_VGPIO3_USB7 */ + PAD_CFG_NF(GPP_VGPIO3_USB7, NONE, DEEP, NF1), + /* GPP_VGPIO3_TS0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS0, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_TS1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS1, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_THC0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC0, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_THC1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC1, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_THC2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC2, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_THC3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC3, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S00 - GPIO */ + PAD_CFG_GPO(GPP_S00, 0, DEEP), + /* GPP_S01 - GPIO */ + PAD_CFG_GPO(GPP_S01, 0, DEEP), + /* GPP_S02 - GPIO */ + PAD_CFG_GPO(GPP_S02, 0, DEEP), + /* GPP_S03 - GPIO */ + PAD_CFG_GPO(GPP_S03, 0, DEEP), + /* GPP_S04 - GPIO */ + PAD_CFG_GPO(GPP_S04, 0, DEEP), + /* GPP_S05 - GPIO */ + PAD_CFG_GPO(GPP_S05, 0, DEEP), + /* GPP_S06 - GPIO */ + PAD_CFG_GPO(GPP_S06, 0, DEEP), + /* GPP_S07 - GPIO */ + PAD_CFG_GPO(GPP_S07, 0, DEEP), + + /* ------- GPIO Group JTAG ------- */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B00 - GPIO */ + PAD_CFG_GPI_INT(GPP_B00, NONE, PLTRST, LEVEL), + /* GPP_B01 - GPIO */ + PAD_CFG_GPO(GPP_B01, 0, DEEP), + /* GPP_B02 - GPIO */ + PAD_CFG_GPO(GPP_B02, 0, DEEP), + /* GPP_B03 - GPIO */ + PAD_CFG_GPO(GPP_B03, 0, DEEP), + /* GPP_B04 - GPIO */ + PAD_CFG_GPO(GPP_B04, 0, DEEP), + /* GPP_B05 - GPIO */ + PAD_CFG_GPO(GPP_B05, 0, DEEP), + /* GPP_B06 - GPIO */ + PAD_CFG_GPO(GPP_B06, 0, DEEP), + /* GPP_B07 - GPIO */ + PAD_CFG_GPO(GPP_B07, 0, DEEP), + /* GPP_B08 - GPIO */ + PAD_CFG_GPO(GPP_B08, 0, DEEP), + /* GPP_B09 - GPIO */ + PAD_CFG_GPO(GPP_B09, 0, DEEP), + /* GPP_B10 - GPIO */ + PAD_CFG_GPO(GPP_B10, 0, DEEP), + /* GPP_B11 - DDSP_HPD2 */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B14, NONE, DEEP, OFF, ACPI), + /* GPP_B15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), + /* GPP_B16 - GPIO */ + PAD_CFG_GPO(GPP_B16, 0, DEEP), + /* GPP_B17 - GPIO */ + PAD_CFG_GPO(GPP_B17, 0, DEEP), + /* GPP_B18 - GPIO */ + PAD_CFG_GPO(GPP_B18, 1, DEEP), + /* GPP_B19 - GPIO */ + PAD_CFG_GPO(GPP_B19, 1, DEEP), + /* GPP_B20 - GPIO */ + PAD_CFG_GPO(GPP_B20, 0, DEEP), + /* GPP_B21 - GPIO */ + PAD_CFG_GPO(GPP_B21, 0, PLTRST), + /* GPP_B22 - GPIO */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), + /* GPP_B23 - GPIO */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + /* GPP_ACI3C0_CLK_LPBK - n/a */ + PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D00 - GPIO */ + PAD_CFG_GPO(GPP_D00, 1, DEEP), + /* GPP_D01 - GPIO */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), + /* GPP_D02 - GPIO */ + PAD_CFG_GPO(GPP_D02, 1, DEEP), + /* GPP_D03 - GPIO */ + PAD_CFG_GPO(GPP_D03, 0, DEEP), + /* GPP_D04 - GPIO */ + PAD_CFG_GPO(GPP_D04, 0, DEEP), + /* GPP_D05 - GPIO */ + PAD_CFG_GPO(GPP_D05, 1, DEEP), + /* GPP_D06 - GPIO */ + PAD_CFG_GPO(GPP_D06, 0, DEEP), + /* GPP_D07 - GPIO */ + PAD_CFG_GPO(GPP_D07, 0, DEEP), + /* GPP_D08 - GPIO */ + PAD_CFG_GPO(GPP_D08, 0, DEEP), + /* GPP_D09 - GPIO */ + PAD_CFG_GPO(GPP_D09, 0, DEEP), + /* GPP_D10 - HDA_BCLK */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + /* GPP_D11 - HDA_SYNC */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), + /* GPP_D12 - HDA_SDO */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), + /* GPP_D13 - HDA_SDI0 */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), + /* GPP_D14 - GPIO */ + PAD_CFG_GPO(GPP_D14, 0, DEEP), + /* GPP_D15 - GPIO */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), + /* GPP_D16 - GPIO */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), + /* GPP_D17 - HDA_RST# */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* GPP_D18 - SRCCLKREQ6# */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* GPP_D19 - SRCCLKREQ7# */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* GPP_D20 - SRCCLKREQ8# */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* GPP_D21 - SRCCLKREQ5# */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), + /* GPP_D22 - n/a */ + PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), + /* GPP_D23 - n/a */ + PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), + /* GPP_BOOTHALT_B - n/a */ + PAD_CFG_NF(GPP_BOOTHALT_B, UP_20K, DEEP, NF1), + + /* ------- GPIO Group VGPIO ------- */ + + /* VGPIO00 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO00, 1, DEEP), + /* VGPIO04 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO04, NONE, DEEP, OFF, ACPI), + /* VGPIO05 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO05, 1, DEEP), + /* VGPIO06 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO06, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO07 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO07, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO08 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO08, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO09 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO09, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO10 - VGPIO10 */ + PAD_CFG_NF(GPP_VGPIO10, NONE, DEEP, NF1), + /* VGPIO11 - VGPIO11 */ + PAD_CFG_NF(GPP_VGPIO11, NONE, DEEP, NF1), + /* VGPIO12 - VGPIO12 */ + PAD_CFG_NF(GPP_VGPIO12, NONE, DEEP, NF1), + /* VGPIO13 - VGPIO13 */ + PAD_CFG_NF(GPP_VGPIO13, NONE, DEEP, NF1), + /* VGPIO18 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO18, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO19 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO19, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO20 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO20, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO21 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO21, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO22 - VGPIO22 */ + PAD_CFG_NF(GPP_VGPIO22, NONE, DEEP, NF1), + /* VGPIO23 - VGPIO23 */ + PAD_CFG_NF(GPP_VGPIO23, NONE, DEEP, NF1), + /* VGPIO24 - VGPIO24 */ + PAD_CFG_NF(GPP_VGPIO24, NONE, DEEP, NF1), + /* VGPIO25 - VGPIO25 */ + PAD_CFG_NF(GPP_VGPIO25, NONE, DEEP, NF1), + /* VGPIO30 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3), + /* VGPIO31 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3), + /* VGPIO32 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3), + /* VGPIO33 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3), + /* VGPIO34 - VGPIO34 */ + PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1), + /* VGPIO35 - VGPIO35 */ + PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1), + /* VGPIO36 - VGPIO36 */ + PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1), + /* VGPIO37 - VGPIO37 */ + PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1), + /* VGPIO40 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO40, NONE, DEEP, NF2), + /* VGPIO41 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO41, NONE, DEEP, NF2), + /* VGPIO42 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO42, NONE, DEEP, NF2), + /* VGPIO43 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO43, NONE, DEEP, NF2), + /* VGPIO44 - VGPIO44 */ + PAD_CFG_NF(GPP_VGPIO44, NONE, DEEP, NF1), + /* VGPIO45 - VGPIO45 */ + PAD_CFG_NF(GPP_VGPIO45, NONE, DEEP, NF1), + /* VGPIO46 - VGPIO46 */ + PAD_CFG_NF(GPP_VGPIO46, NONE, DEEP, NF1), + /* VGPIO47 - VGPIO47 */ + PAD_CFG_NF(GPP_VGPIO47, NONE, DEEP, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/novacustom/mtl-h/gpio_early.c b/src/mainboard/novacustom/mtl-h/gpio_early.c new file mode 100644 index 0000000..c47883e --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + /* GPP_C00 - SMBCLK */ + PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1), + /* GPP_C01 - SMBDATA */ + PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/novacustom/mtl-h/hda_verb.c b/src/mainboard/novacustom/mtl-h/hda_verb.c new file mode 100644 index 0000000..cd7493e --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/hda_verb.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x1558a763, /* Subsystem ID */ + 13, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558a763), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + + /* Intel Meteor Lake HDMI */ + 0x8086281d, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h new file mode 100644 index 0000000..57924a6 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c new file mode 100644 index 0000000..cd7031b --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/ramstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/dasharo/ec/acpi.h> +#include <mainboard/gpio.h> +#include <smbios.h> +#include <soc/ramstage.h> + +const char *smbios_system_sku(void) +{ + return "Not Applicable"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; + + // Pinmux configuration + params->CnviRfResetPinMux = 0x194CE404; // GPP_F04 + params->CnviClkreqPinMux = 0x394CE605; // GPP_F05 + + params->LidStatus = dasharo_ec_get_lid_state(); +} diff --git a/src/mainboard/novacustom/mtl-h/romstage.c b/src/mainboard/novacustom/mtl-h/romstage.c new file mode 100644 index 0000000..8fdd9ec --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/romstage.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const bool half_populated = false; + + static const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR5, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_ULT_ULX, + }; + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { + .addr_dimm[0] = 0x52, + }, + }, + }; + + memcfg_init(mupd, &mem_config, &dimm_module_spd_info, half_populated); +} diff --git a/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd b/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd new file mode 100644 index 0000000..18a5027 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd @@ -0,0 +1,49 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K + SI_GBE 8K + SI_ME + } + SI_BIOS { + RW_SECTION_A 7M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + BOOTSPLASH(CBFS) 1M + } + + RW_SECTION_B 7M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + + WP_RO 7M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 256 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +}