[coreboot-gerrit] Change in coreboot[master]: arch/x86: Remove 64KiB bootblock limit

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47193 )

Change subject: arch/x86: Remove 64KiB bootblock limit
......................................................................

arch/x86: Remove 64KiB bootblock limit

X86 CPU start by executing the reset vector in 16bit real mode. The
first instruction, called the reset vector is a jump instruction.
Since this is 16bit the jump needs to remain in the 64KiB section.
This adds a section to the linker script for code that needs to remain
close enough to the reset vector. As soon as we are in 32bit protected
mode we can jump anywhere else in the bootblock. This removes the
64KiB limit on the C_ENV_BOOTBLOCK_SIZE.

For systems where the SIPI vector is in ROM the alignment of the
_start16bit symbol is handled in the linker script instead of the
assembly code.

Change-Id: I192fd08311fccf2e73a70799de2b028a9c8c4a40
Signed-off-by: Arthur Heymans 
---
M src/arch/x86/bootblock_crt0.S
M src/cpu/x86/16bit/entry16.inc
M src/cpu/x86/16bit/reset16.ld
3 files changed, 27 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47193/1

diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S
index 3f41464..389dd55 100644
--- a/src/arch/x86/bootblock_crt0.S
+++ b/src/arch/x86/bootblock_crt0.S
@@ -10,16 +10,18 @@

#include <cpu/x86/cr.h>

-.section .text
-
 /*
  * Include the old code for reset vector and protected mode entry. That code has
  * withstood the test of time.
  */
+.section ".bootblock.top", "ax", @progbits
 #include <cpu/x86/16bit/entry16.inc>
 #include <cpu/x86/16bit/reset16.inc>
 #include <cpu/x86/32bit/entry32.inc>
+	jmp continue_text

+.section .text
+continue_text:
 #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP)

/* Wait for a JTAG debugger to break in and set EBX non-zero */
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 13d12be..86c14a0 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -31,7 +31,6 @@
 /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
  * Startup IPI message without RAM.
  */
-.align 4096
 .code16
 .globl _start16bit
 .type _start16bit, @function
diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld
index b90dd04..97e70b9 100644
--- a/src/cpu/x86/16bit/reset16.ld
+++ b/src/cpu/x86/16bit/reset16.ld
@@ -2,11 +2,27 @@

/* _RESET_VECTOR: typically the top of the ROM */

+#define ALIGN_DOWN(loc, size) ((loc) / (size) * (size))
+
+#define REALMODE_ALIGNMENT (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 16)
+#define RESERVED_BELOW_RESET 0xf0
+
 SECTIONS {
    /* Trigger an error if I have an unuseable start address */
    _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0;
    _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report.");

+	.bogus ROMLOC_MIN : {
+		. = ALIGN(4);
+	}
+
+	.bootblock_top . : {
+		. = ALIGN(REALMODE_ALIGNMENT);
+		_realmode = .;
+		*(.bootblock.top);
+		_erealmode = .;
+	}
+
    . = CONFIG_X86_RESET_VECTOR;
    .reset . : {
    	*(.reset);
@@ -14,3 +30,10 @@
    	BYTE(0x00);
    }
 }
+
+EARLYASM_SIZE = (_erealmode - _realmode);
+/* Assume that 0xf0 below the reset vector (size 0x10), so 0x100 in total is
+ * not available for code.
+ */
+ROMLOC_MIN = ALIGN_DOWN(CONFIG_X86_RESET_VECTOR - RESERVED_BELOW_RESET - EARLYASM_SIZE, \
+	REALMODE_ALIGNMENT);