Attention is currently required from: Paul Menzel, Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62698 )
Change subject: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes ......................................................................
Patch Set 1:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62698/comment/764c582a_4f11cd4c PS1, Line 7: Use 512 bytes for SPD buffer
Maybe: […]
Sure, fine with me.
https://review.coreboot.org/c/coreboot/+/62698/comment/8eb5d0ab_307784de PS1, Line 9: DDR4 SPD data needs to be 512 byte to comply with the spec. : Though there is no vital timing data used beyond 256 byte there are some : part information which will be used to show the part info in the : coreboot log. If the buffer is too small this log shows garbage.
Please add a blank line between paragraphs.
Ack
https://review.coreboot.org/c/coreboot/+/62698/comment/248b5e1a_338e98ca PS1, Line 13:
Maybe give an example line with garbled data?
I do not use this part number hence cannot provide an example.
File src/mainboard/siemens/mc_ehl/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62698/comment/7c75d7f6_c0ebf033 PS1, Line 28: hexdump(spd_data, sizeof(spd_data));
Is this debugging leftover?
Ups, yes. This one slipped in, will remove.