[coreboot-gerrit] Change in coreboot[master]: mb/ti/beaglebone: Initialize DDR3

[Sam Lewis (Code Review)]

Hello build bot (Jenkins), Arthur Heymans,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44387

to look at the new patch set (#10).

Change subject: mb/ti/beaglebone: Initialize DDR3
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mb/ti/beaglebone: Initialize DDR3

Adds initialisation of 512MB of DDR memory on the BBB to the romstage.
The parameters for the DDR peripherals are taken from U-Boot.

TEST: Booted from romstage into ramstage. Also successfully managed to
run the "ram_check" in lib.h.

Change-Id: I692bfd913c8217a78d073d19c5344c9bb40722a8
Signed-off-by: Sam Lewis 
---
M src/mainboard/ti/beaglebone/Kconfig
A src/mainboard/ti/beaglebone/ddr3.h
M src/mainboard/ti/beaglebone/romstage.c
3 files changed, 76 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/44387/10