[coreboot-gerrit] Change in coreboot[master]: rk3399: clock: Fix style for rkclk_ddr_reset()

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51080 )

Change subject: rk3399: clock: Fix style for rkclk_ddr_reset()
......................................................................

rk3399: clock: Fix style for rkclk_ddr_reset()

This function should be using the RK_CLRSETBITS() macros to access the
special Rockchip write-mask registers, like the rest of our code. Also,
there were already existing bit field definitions for these bits that
should be used (although it makes sense to adjust them a bit to allow
passing in the channel number).

Signed-off-by: Julius Werner 
Change-Id: If1f5c06aabb16045d890df3bbd271f08a2cdf390
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51080
Reviewed-by: Moritz Fischer 
Reviewed-by: Angel Pons 
Reviewed-by: Patrick Georgi 
Tested-by: build bot (Jenkins) 
---
M src/soc/rockchip/rk3399/clock.c
1 file changed, 6 insertions(+), 15 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve
  Moritz Fischer: Looks good to me, but someone else must approve

diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 182e398..75af695b 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -249,14 +249,8 @@
    CLK_I2C3_DIV_CON_SHIFT		= 0,

/* CRU_SOFTRST_CON4 */
-	RESETN_DDR0_REQ_MASK		= 1,
-	RESETN_DDR0_REQ_SHIFT		= 8,
-	RESETN_DDRPHY0_REQ_MASK		= 1,
-	RESETN_DDRPHY0_REQ_SHIFT	= 9,
-	RESETN_DDR1_REQ_MASK		= 1,
-	RESETN_DDR1_REQ_SHIFT		= 12,
-	RESETN_DDRPHY1_REQ_MASK		= 1,
-	RESETN_DDRPHY1_REQ_SHIFT	= 13,
+#define RESETN_DDR_REQ_SHIFT(ch)	(8 + (ch) * 4)
+#define RESETN_DDRPHY_REQ_SHIFT(ch)	(9 + (ch) * 4)
 };

#define VCO_MAX_KHZ	(3200 * (MHz / KHz))
@@ -650,14 +644,11 @@
    	rkclk_set_dpllssc(&dpll_cfg);
 }

-#define CRU_SFTRST_DDR_CTRL(ch, n)	((1 << 16 | (n)) << (8 + (ch) * 4))
-#define CRU_SFTRST_DDR_PHY(ch, n)	((1 << 16 | (n)) << (9 + (ch) * 4))
-
-void rkclk_ddr_reset(u32 channel, u32 ctl, u32 phy)
+void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy)
 {
-	write32(&cru_ptr->softrst_con[4],
-		CRU_SFTRST_DDR_CTRL(channel, ctl) |
-		CRU_SFTRST_DDR_PHY(channel, phy));
+	write32(&cru_ptr->softrst_con[4], RK_CLRSETBITS(
+		1 << RESETN_DDR_REQ_SHIFT(ch) | 1 << RESETN_DDRPHY_REQ_SHIFT(ch),
+		ctl << RESETN_DDR_REQ_SHIFT(ch) | phy << RESETN_DDRPHY_REQ_SHIFT(ch)));
 }

#define SPI_CLK_REG_VALUE(bus, clk_div) \