[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/trulo: Streamlines WP gpio pin configuration

[Dinesh Gehlot (Code Review)]

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85937?usp=email )

Change subject: mb/google/trulo: Streamlines WP gpio pin configuration
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mb/google/trulo: Streamlines WP gpio pin configuration

This patch streamlines the configuration of the write protect pin,
eliminating driver overhead by using generic PAD_CFG_GPI.

BUG=b:386741705
TEST=Able to build google/truloti

Change-Id: I3621dfd6b80215a2fe6a468e852189df0bed86a2
Signed-off-by: Dinesh Gehlot 
---
M src/mainboard/google/brya/variants/trulo/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85937/1

diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c
index 8f0ad94..f06ea18 100644
--- a/src/mainboard/google/brya/variants/trulo/gpio.c
+++ b/src/mainboard/google/brya/variants/trulo/gpio.c
@@ -165,7 +165,7 @@
    /* E2  : THC0_SPI1_IO3 ==> RAM_ID0 */
    PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
    /* E3  : PROC_GP0 ==> SOC_WP_OD */
-	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E3, NONE, LOCK_CONFIG),
+	PAD_CFG_GPI(GPP_E3, NONE, DEEP),
    /* E4  : NC */
    PAD_NC(GPP_E4, NONE),
    /* E5  : NC */
@@ -417,7 +417,7 @@
    /* A17 : GPP_A17 ==> GSC_SOC_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
    /* E3 : PROC_GP0 ==> SOC_WP_OD */
-	PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_E3, NONE, DEEP),
    /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
    PAD_CFG_GPI(GPP_F18, NONE, DEEP),
    /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */