Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60731 )
Change subject: soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config ......................................................................
soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config
Since Tiger Lake platform, the HECI1 device can be disabled on Alder Lake platform using two different mechanism: A. Using PMC IPC command 0xA9. B. Sending SBI message under SMM.
In current scope of Alder Lake the default implementation is using (B) sending sbi message under SMM. A follow up patch to add the possible options and let platform to choose the applicable one.
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Default enable HECI1 device in `chipset.cb` to ensure the HECI1 device can undergo the PCI enumeration and later based on the mainboard policy the HECI1 device can be disabled.
Mainboards that choose to make HECI1 enable during boot don't override `DISABLE_HECI1_AT_PRE_BOOT` config.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60731 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/smihandler.c 10 files changed, 4 insertions(+), 30 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 346b98e..a36c849 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -17,9 +17,6 @@ # DPTF enable register "dptf_enable" = "1"
- # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi BT register "CnviBtCore" = "true"
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 7323b10..ee0fbce 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -19,9 +19,6 @@
register "tcc_offset" = "10" # TCC of 90
- # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi BT register "CnviBtCore" = "true"
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 8f60e42..9bd99b1 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -8,9 +8,6 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E"
- # Enable HECI1 interface - register "HeciEnabled" = "1" - # FSP configuration
# Enable CNVi BT diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index ab99830..c637ec3 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -18,9 +18,6 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E"
- # Enable HECI1 communication - register "HeciEnabled" = "1" - # FSP configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0 register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1 diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index cec0422..f013596 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -8,9 +8,6 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E"
- # Enable HECI1 interface - register "HeciEnabled" = "1" - # FSP configuration
# Enable CNVi BT diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 5757392..63d3da4 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -16,9 +16,6 @@ register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}"
- # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi Bluetooth register "CnviBtCore" = "true"
diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 513e3b8..cf2e270 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -8,9 +8,6 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E"
- # Enable HECI1 interface - register "HeciEnabled" = "1" - device domain 0 on device ref pcie5 on end device ref igpu on end diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index e997e78..a5543d6 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -314,10 +314,6 @@ } IgdDvmt50PreAlloc; uint8_t SkipExtGfxScan;
- /* HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS */ - uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable;
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 7de8f09..09dc970 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -175,7 +175,7 @@ device pci 15.1 alias i2c1 off end device pci 15.2 alias i2c2 off end device pci 15.3 alias i2c3 off end - device pci 16.0 alias heci1 off end + device pci 16.0 alias heci1 on end device pci 16.1 alias heci2 off end device pci 16.2 alias ide_r off end device pci 16.3 alias kt off end diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c index 5b53038..d9ea96a 100644 --- a/src/soc/intel/alderlake/smihandler.c +++ b/src/soc/intel/alderlake/smihandler.c @@ -16,11 +16,10 @@ */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_alderlake_config *config; + if (!CONFIG(HECI_DISABLE_USING_SMM)) + return;
- config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci_disable(); }