[coreboot-gerrit] Change in ...coreboot[master]: WIP: fixup

[Julius Werner (Code Review)]

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32537

Change subject: WIP: fixup
......................................................................

WIP: fixup

DO NOT REVIEW (yet)

Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner 
---
M src/drivers/pc80/rtc/mc146818rtc.c
M src/lib/Makefile.inc
M src/soc/rockchip/common/spi.c
3 files changed, 7 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32537/1

diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c
index 99079b9..6e37cd2 100644
--- a/src/drivers/pc80/rtc/mc146818rtc.c
+++ b/src/drivers/pc80/rtc/mc146818rtc.c
@@ -39,6 +39,9 @@
 #define LB_CKS_LOC		0
 #endif

+/* Don't warn for checking >= LB_CKS_RANGE_START even though it may be 0. */
+#pragma GCC diagnostic ignored "-Wtype-limits"
+
 #include <smp/spinlock.h>

#if (defined(__PRE_RAM__) &&	\
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 1350152..7cf0a62 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -322,9 +322,9 @@

endif # CONFIG_RAMSTAGE_LIBHWBASE

+ifeq ($(CONFIG_GENERIC_SPD_BIN),y)
 romstage-y += spd_bin.c

-ifeq ($(CONFIG_GENERIC_SPD_BIN),y)
 LIB_SPD_BIN = $(obj)/spd.bin

LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c
index 98016c0..e929419 100644
--- a/src/soc/rockchip/common/spi.c
+++ b/src/soc/rockchip/common/spi.c
@@ -96,7 +96,7 @@

void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
 {
-	assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves));
+	assert(bus < ARRAY_SIZE(rockchip_spi_slaves));
    struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs;
    unsigned int ctrlr0 = 0;

@@ -134,13 +134,13 @@

void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns)
 {
-	assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves));
+	assert(bus < ARRAY_SIZE(rockchip_spi_slaves));
    struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs;
    unsigned int rsd;

/* Rxd Sample Delay */
    rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8);
-	assert(rsd >= 0 && rsd <= 3);
+	assert(rsd <= 3);
    clrsetbits_le32(&regs->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET,
    		rsd << SPI_RXDSD_OFFSET);
 }