[coreboot-gerrit] Change in coreboot[master]: arch/x86: Cache the TSEG region at the top of ram

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34995 )

Change subject: arch/x86: Cache the TSEG region at the top of ram
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Patch Set 4:

Aaron, please visit CB:34805 patchset #6 comments and how you wish to address the alignment requirement about parameters passed to postcar_frame_setup_top_of_dram_usage(), if it will be extended to call set_var_mtrr().

Subrata, can we have cbmem -t for this commit posted as well. My concern is that after all this work, POSTCAR_STAGE=y is still the better performing solution, winning POSTCAR_STAGE=n by some 7 ms.