HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16782
-gerrit
commit 27f58ec4c822307b798193a380c2171fd0c46fc2 Author: Elyes HAOUAS ehaouas@noos.fr Date: Wed Sep 28 19:56:00 2016 +0200
mainboard/iwill/dk8_htx: Use tabs for indents
Change-Id: I303270a45171dda88b7661e3797fd3724e3b055f Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/mainboard/iwill/dk8_htx/acpi_tables.c | 176 +++++++++++++++--------------- src/mainboard/iwill/dk8_htx/mb_sysconf.h | 18 +-- src/mainboard/iwill/dk8_htx/romstage.c | 60 +++++----- 3 files changed, 127 insertions(+), 127 deletions(-)
diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index 5b2b2b0..b9e8468 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -26,11 +26,11 @@ unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18;
- struct mb_sysconf_t *m; + struct mb_sysconf_t *m;
get_bus_conf();
- m = sysconf.mb; + m = sysconf.mb;
/* create all subtables for processors */ current = acpi_create_madt_lapics(current); @@ -39,75 +39,75 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111, IO_APIC_ADDR, 0);
- /* Write all 8131 IOAPICs */ - { - device_t dev; - struct resource *res; - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, - res->base, gsi_base ); + /* Write all 8131 IOAPICs */ + { + device_t dev; + struct resource *res; + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, + res->base, gsi_base ); gsi_base+=4;
- } - } - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, - res->base, gsi_base ); - gsi_base+=4; - } - } - - int i; - int j = 0; - - for(i = 1; i< sysconf.hc_possible_num; i++) { + } + } + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, + res->base, gsi_base ); + gsi_base+=4; + } + } + + int i; + int j = 0; + + for(i = 1; i< sysconf.hc_possible_num; i++) { unsigned d = 0; - if(!(sysconf.pci1234[i] & 0x1) ) continue; - // 8131 need to use +4 + if(!(sysconf.pci1234[i] & 0x1) ) continue; + // 8131 need to use +4
- switch (sysconf.hcid[i]) { - case 1: + switch (sysconf.hcid[i]) { + case 1: d = 7; break; case 3: d = 4; break; } - switch (sysconf.hcid[i]) { - case 1: + switch (sysconf.hcid[i]) { + case 1: case 3: - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], - res->base, gsi_base ); - gsi_base+=d; - } - } - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], - res->base, gsi_base ); - gsi_base+=d; - - } - } - break; - } - - j++; - } - - } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], + res->base, gsi_base ); + gsi_base+=d; + } + } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], + res->base, gsi_base ); + gsi_base+=d; + + } + } + break; + } + + j++; + } + + }
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) current, 0, 0, 2, 5 ); @@ -117,8 +117,8 @@ unsigned long acpi_fill_madt(unsigned long current) /* 5 mean: 0101 --> Edge-triggered, Active high*/
- /* create all subtables for processors */ - current = acpi_create_madt_lapic_nmis(current, 5, 1); + /* create all subtables for processors */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); /* 1: LINT1 connect to NMI */
@@ -142,36 +142,36 @@ unsigned long mainboard_write_acpi_tables(device_t device, start = ALIGN(start, 16); current = start;
- //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table + //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
- for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink const char *file_name; - if((sysconf.pci1234[i] & 1) != 1 ) continue; - uint8_t c; - if(i < 7) { - c = (uint8_t) ('4' + i - 1); - } - else { - c = (uint8_t) ('A' + i - 1 - 6); - } - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt - current = ALIGN(current, 8); - ssdtx = (acpi_header_t *)current; - switch(sysconf.hcid[i]) { - case 1: //8132 + if((sysconf.pci1234[i] & 1) != 1 ) continue; + uint8_t c; + if(i < 7) { + c = (uint8_t) ('4' + i - 1); + } + else { + c = (uint8_t) ('A' + i - 1 - 6); + } + printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt + current = ALIGN(current, 8); + ssdtx = (acpi_header_t *)current; + switch(sysconf.hcid[i]) { + case 1: //8132 file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; - break; - case 2: //8151 + break; + case 2: //8151 file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; - break; + break; case 3: //8131 file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; - break; - default: + break; + default: //HTX no io apic file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; break; - } + } p = cbfs_boot_map_with_leak( file_name, CBFS_TYPE_RAW, &p_size); @@ -181,11 +181,11 @@ unsigned long mainboard_write_acpi_tables(device_t device, memcpy(ssdtx, p, sizeof(acpi_header_t)); current += ssdtx->length; memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length); - acpi_add_table(rsdp,ssdtx); - } + update_ssdtx((void *)ssdtx, i); + ssdtx->checksum = 0; + ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length); + acpi_add_table(rsdp,ssdtx); + }
return current; } diff --git a/src/mainboard/iwill/dk8_htx/mb_sysconf.h b/src/mainboard/iwill/dk8_htx/mb_sysconf.h index ef3dace..4933d48 100644 --- a/src/mainboard/iwill/dk8_htx/mb_sysconf.h +++ b/src/mainboard/iwill/dk8_htx/mb_sysconf.h @@ -9,18 +9,18 @@ struct mb_sysconf_t { unsigned char bus_8111_0; unsigned char bus_8111_1;
- unsigned char bus_8132a[7][3]; + unsigned char bus_8132a[7][3];
- unsigned char bus_8151[7][2]; + unsigned char bus_8151[7][2];
- unsigned apicid_8111; - unsigned apicid_8132_1; - unsigned apicid_8132_2; - unsigned apicid_8132a[7][2]; + unsigned apicid_8111; + unsigned apicid_8132_1; + unsigned apicid_8132_2; + unsigned apicid_8132a[7][2];
- unsigned sbdn3; - unsigned sbdn3a[7]; - unsigned sbdn5[7]; + unsigned sbdn3; + unsigned sbdn3a[7]; + unsigned sbdn5[7];
};
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index fa0c11c..c1c141e 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -51,7 +51,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); }
#include <northbridge/amd/amdk8/amdk8.h> @@ -77,10 +77,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) };
struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0;
- if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- setup_mb_resource_map(); + setup_mb_resource_map();
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
@@ -99,47 +99,47 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ - start_other_cores(); + start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif
/* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } #endif
needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo);
- // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + }
allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus(); @@ -151,13 +151,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ - init_timer(); // Need to use TMICT to synchronize FID/VID + /* all ap stopped? */ + init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0 - dump_pci_devices(); + dump_pci_devices(); #endif
- post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now }