[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, TangYiwei, Tim Chu.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email )

Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes
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Patch Set 21:

(3 comments)

File src/soc/intel/xeon_sp/chip_gen6.c:

https://review.coreboot.org/c/coreboot/+/81316/comment/1a99123e_0c0217d8 :
PS21, Line 34: }
Note, you could avoid the late HOB lookup by adding the resources already
when the domains are created (this is generally fine when the resources
are not read from hardware). Basically what we did with the SPR IOAT
domains.

Of course, you could also read hardware registers instead, then we wouldn't
rely that much on HOB information.

https://review.coreboot.org/c/coreboot/+/81316/comment/dc003e92_56272c50 :
PS21, Line 57: 			res->flags = IORESOURCE_SUBTRACTIVE;
In hardware, there's virtually always only one subtractive resource of a type.
Are you sure about this? it might conflict with the resource added below (line 73).

Generally, all the semantic changes here compared to gen1 seem odd to me. Did this
really change? Does domain0 always have subtractive resource windows (also mem and prefmem)?

https://review.coreboot.org/c/coreboot/+/81316/comment/8c453bcd_bfd2d892 :
PS21, Line 119: void iio_pci_domain_read_resources(struct device *dev)
Why is this an external API?