Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42737 )
Change subject: soc/intel/cannonlake: Add UWES ASL into xhci.asl
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Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42737/3/src/soc/intel/cannonlake/ac...
File src/soc/intel/cannonlake/acpi/xhci.asl:
https://review.coreboot.org/c/coreboot/+/42737/3/src/soc/intel/cannonlake/ac...
PS3, Line 70: 0x3FF
There are 12 USB2 ports listed below (compared to 10 for skylake) so I suspect this should be 0xFFF for cannonlake.
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