[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Configure voltage margining policies

[Krzysztof M Sywula (Code Review)]

Hello Thejaswani Putta, Patrick Rudolph, Subrata Banik, Roy Mingi Park, Duncan Laurie, Bora Guvendik, build bot (Jenkins), Lijian Zhao,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32026

to look at the new patch set (#3).

Change subject: soc/intel/cannonlake: Configure voltage margining policies
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soc/intel/cannonlake: Configure voltage margining policies

For systems that integrate GbE controllers, following parameters should be configured:
SlpS0WithGbeSupport: enable PchPmSlpS0VmRuntimeControl: disable,
PchPmSlpS0Vm070VSupport: disable, PchPmSlpS0Vm075VSupport: disable.

TEST=boot on any GbE supported WHL platform

Change-Id: I02aaf0b77b8fc1555a3a424c02acfada21707d0e
Signed-off-by: Krzysztof Sywula 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 17 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32026/3