[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add timestamp for cse_fw_sync

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60135 )

Change subject: soc/intel/alderlake: Add timestamp for cse_fw_sync
......................................................................

soc/intel/alderlake: Add timestamp for cse_fw_sync

The patch add timestamp around cse_fw_sync().

TEST=Verified on Brya, cbmem -t:

948:starting CSE firmware sync		1,381,577 (45,227)
 949:finished CSE firmware sync		1,459,513 (77,936)

Signed-off-by: Sridhar Siricilla 
Change-Id: Idba11417e0fc7c18d0d938a4293ec3aff1537fb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60135
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Maulik V Vaghela 
---
M src/soc/intel/alderlake/romstage/romstage.c
1 file changed, 5 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Maulik V Vaghela: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index b9d08c8..ae83d49 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -16,6 +16,7 @@
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
 #include <cpu/intel/cpu_ids.h>
+#include <timestamp.h>
 #include <string.h>

#define FSP_SMBIOS_MEMORY_INFO_GUID	\
@@ -135,8 +136,11 @@

s3wake = pmc_fill_power_state(ps) == ACPI_S3;

-	if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake)
+	if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) {
+		timestamp_add_now(TS_START_CSE_FW_SYNC);
    	cse_fw_sync();
+		timestamp_add_now(TS_END_CSE_FW_SYNC);
+	}

/*
     * Set low maximum temp threshold value used for dynamic thermal sensor