Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69887 )
(
3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/mc_ehl2: Enable downshift for Marvell PHYs ......................................................................
mb/siemens/mc_ehl2: Enable downshift for Marvell PHYs
Set downshift counter to 2 for all Marvell PHYs on this mainboard before the PHY downshifts to the next highest speed.
Change-Id: I32b5f25a3e1e0f962dff3110143e236992ef8e7d Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/69887 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 19 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 8090927..e1c2972 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -191,6 +191,7 @@ register "led_1_ctrl" = "1" # INTn is routed to LED[2] pin register "enable_int" = "true" + register "downshift_cnt" = "2" device mdio 0 on # PHY address ops m88e1512_ops end @@ -206,6 +207,7 @@ register "led_1_ctrl" = "1" # INTn is routed to LED[2] pin register "enable_int" = "true" + register "downshift_cnt" = "2" device mdio 1 on # PHY address ops m88e1512_ops end @@ -224,6 +226,7 @@ register "led_1_ctrl" = "1" # INTn is routed to LED[2] pin register "enable_int" = "true" + register "downshift_cnt" = "2" device mdio 1 on # PHY address ops m88e1512_ops end