Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38739 )
Change subject: mb/google/dedede: Turn on ESPI device in devicetree ......................................................................
mb/google/dedede: Turn on ESPI device in devicetree
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I12a63e5776619e5a7684cf1edad78b0fd6fac12c Reviewed-on: https://review.coreboot.org/c/coreboot/+/38739 Reviewed-by: Justin TerAvest teravest@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 2 files changed, 13 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Justin TerAvest: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index aedd32f..44d9ca2 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -56,7 +56,11 @@ device pci 1e.1 off end # UART 1 device pci 1e.2 off end # GSPI 0 device pci 1e.3 off end # GSPI 1 - device pci 1f.0 off end # eSPI Interface + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI Interface device pci 1f.1 off end # P2SB device pci 1f.2 off end # Power Management Controller device pci 1f.3 off end # Intel HDA/cAVS diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 6c95a1d..0908412 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -13,7 +13,14 @@
/* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* ToDo: Fill gpio configuration */ + /* GPP_A0 thru GPP_A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 */ + /* A1 : ESPI_IO1 */ + /* A2 : ESPI_IO2 */ + /* A3 : ESPI_IO3 */ + /* A4 : ESPI_CS# */ + /* A5 : ESPI_CLK */ + /* A6 : ESPI_RESET_L */ };
/* Early pad configuration in bootblock */