[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Expose FSP params to be adjusted from devicetre...

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32026 )

Change subject: soc/intel/cannonlake: Expose FSP params to be adjusted from devicetree.cb
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Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... 
PS1, Line 169: PchPmSlpS0VmRuntimeControl
> Unless we have hardware/electrical engineer say otherwise, I'm gonna go with what google offers:

Can you please get confirmation from hardware/FSP team about what voltage margining really means in this case w.r.t. S0ix? My past experience with voltage margining on KBL was very different than the definitions outlined above.