Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58043 )
Change subject: soc/intel: deduplicate acpi_fill_soc_wake ......................................................................
soc/intel: deduplicate acpi_fill_soc_wake
The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in common code.
Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5 Signed-off-by: Michael Niewöhner foss@mniewoehner.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/tigerlake/acpi.c 8 files changed, 1 insertion(+), 105 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index b28ec12..9f4fa88 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -280,21 +280,6 @@ sa_fill_gnvs(gnvs); }
-uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index b6d61b1..8f5dd12 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -95,21 +95,6 @@ sa_fill_gnvs(gnvs); }
-uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_LOW; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 7095120..d0f3874 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -185,21 +185,6 @@ sa_fill_gnvs(gnvs); }
-uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index c21a861..9bfb91a 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -218,6 +218,7 @@ * powerbtn or any other wake source like lidopen, key board press etc. */ pm1_en = ps->pm1_en; + pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
pm1_en = acpi_fill_soc_wake(pm1_en, ps);
diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index abbb1ec..7531331 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -249,21 +249,6 @@ sa_fill_gnvs(gnvs); }
-uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index cac2138..fa6d038 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -180,21 +180,6 @@ sa_fill_gnvs(gnvs); }
-uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index b4efddb..cc7b8ae6 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -260,21 +260,6 @@ sa_fill_gnvs(gnvs); }
-uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH; diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 1a8ccb9..e560f11 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -275,21 +275,6 @@ sa_fill_gnvs(gnvs); }
-uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, - const struct chipset_power_state *ps) -{ - /* - * WAK_STS bit is set when the system is in one of the sleep states - * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting - * this bit, the PMC will transition the system to the ON state and - * can only be set by hardware and can only be cleared by writing a one - * to this bit position. - */ - - generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; - return generic_pm1_en; -} - int soc_madt_sci_irq_polarity(int sci) { return MP_IRQ_POLARITY_HIGH;
8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.