[coreboot-gerrit] [S] Change in coreboot[main]: soc/amd/cezanne: add option to disable I2S master clock output of FCH

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85865?usp=email )

(

4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/amd/cezanne: add option to disable I2S master clock output of FCH
......................................................................

soc/amd/cezanne: add option to disable I2S master clock output of FCH

Add a devicetree option to disable the 48MHz clock output of the FCH
when an I2S audio codec uses a separate oscillator for its 48 MHz
master clock instead of the FCH clock output. This code was ported
from the Picasso code base.

Change-Id: I0c1bee121f528d28d591dace260507b345dfec26
Signed-off-by: Anand Vaikar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85865
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
---
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
2 files changed, 12 insertions(+), 2 deletions(-)

Approvals:
  Felix Held: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index a8b7f22..738282f 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -108,6 +108,9 @@
    	uint8_t tx_eq_post;
    	uint8_t tx_vboost_lvl;
    } edp_tuningset;
+
+	/* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
+	bool acp_i2s_use_external_48mhz_osc;
 };

#endif /* CEZANNE_CHIP_H */
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index b9f529d..0690eb7 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -83,8 +83,15 @@
 static void fch_clk_output_48Mhz(void)
 {
    uint32_t ctrl = misc_read32(MISC_CLK_CNTL0);
-	/* Enable BP_X48M0 Clock Output */
-	ctrl |= BP_X48M0_OUTPUT_EN;
+	const struct soc_amd_cezanne_config *cfg = config_of_soc();
+
+	/* If using external clock source for I2S, disable the internal clock output */
+	if (cfg->acp_i2s_use_external_48mhz_osc &&
+		cfg->common_config.acp_config.acp_pin_cfg == I2S_PINS_I2S_TDM)
+		ctrl &= ~BP_X48M0_OUTPUT_EN;
+	else
+		ctrl |= BP_X48M0_OUTPUT_EN;
+
    /* Disable clock output in S0i3 */
    ctrl |= BP_X48M0_S0I3_DIS;
    misc_write32(MISC_CLK_CNTL0, ctrl);