[coreboot-gerrit] Change in coreboot[master]: soc/amd: add and use fch_enable_hpet_decode

[Martin Roth (Code Review)]

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50512 )

Change subject: soc/amd: add and use fch_enable_hpet_decode
......................................................................

soc/amd: add and use fch_enable_hpet_decode

On Picasso we missed setting this bit in coreboot and since the default
after reset is 0, we had to rely on the FSP to set this bit. Stoneyridge
and Cezanne have the HPET decode enable bit in the same position in the
same register. In the ACPI table entry written by
southbridge_write_acpi_tables the HPET entry gets added, so we should
make sure that we enable the decode.

TEST=HPET still works on Mandolin.

Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50512
Reviewed-by: Raul Rangel 
Reviewed-by: Marshall Dawson 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/common/block/acpimmio/mmio_util.c
M src/soc/amd/common/block/include/amdblocks/acpimmio.h
M src/soc/amd/common/block/smbus/sm.c
3 files changed, 13 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved
  Raul Rangel: Looks good to me, approved

diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c
index a19a28b..3a86aaf 100644
--- a/src/soc/amd/common/block/acpimmio/mmio_util.c
+++ b/src/soc/amd/common/block/acpimmio/mmio_util.c
@@ -79,6 +79,14 @@
    pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | FCH_IOAPIC_EN);
 }

+void fch_configure_hpet(void)
+{
+	uint32_t reg = pm_read32(PM_DECODE_EN);
+	reg |=  HPET_EN | HPET_MSI_EN;
+	reg &= ~HPET_WIDTH_SEL; /* 32 bit HPET */
+	pm_write32(PM_DECODE_EN, reg);
+}
+
 /* PM registers are accessed a byte at a time via CD6/CD7 */
 uint8_t pm_io_read8(uint8_t reg)
 {
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 19decdd..a9a6986 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -15,8 +15,11 @@
  * newer SoCs, but not for the generations with separate FCH or Kabini.
  */
 #define PM_DECODE_EN			0x00
+#define   HPET_MSI_EN			(1 << 29)
+#define   HPET_WIDTH_SEL		(1 << 28) /* 0=32bit, 1=64bit */
 #define   SMBUS_ASF_IO_BASE_SHIFT	8
 #define   SMBUS_ASF_IO_BASE_MASK	(0xff << SMBUS_ASF_IO_BASE_SHIFT)
+#define   HPET_EN			(1 << 6) /* decode HPET MMIO at 0xfed00000 */
 #define   FCH_IOAPIC_EN			(1 << 5)
 #define   SMBUS_ASF_IO_EN		(1 << 4)
 #define   CF9_IO_EN			(1 << 1)
@@ -77,6 +80,7 @@
 void fch_enable_legacy_io(void);
 void fch_io_enable_legacy_io(void);
 void fch_enable_ioapic_decode(void);
+void fch_configure_hpet(void);

/* Access PM registers using IO cycles */
 uint8_t pm_io_read8(uint8_t reg);
diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c
index 0b219e0..b1b3db6 100644
--- a/src/soc/amd/common/block/smbus/sm.c
+++ b/src/soc/amd/common/block/smbus/sm.c
@@ -13,6 +13,7 @@
 {
    fch_enable_ioapic_decode();
    setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
+	fch_configure_hpet();
 }

static u32 get_sm_mmio(struct device *dev)