[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Add UPDs for support eDP phy tunning adjust

[chris wang (Code Review)]

Hello Chris Wang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/48731

to review the following change.

Change subject: soc/amd/picasso: Add UPDs for support eDP phy tunning adjust
......................................................................

soc/amd/picasso: Add UPDs for support eDP phy tunning adjust

Add UPDs for eDP phy tunning adjust

BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp

Signed-off-by: Chris Wang 
Change-Id: I6df063f828447841ac9a6dba00a4aad2001f04df
---
M src/vendorcode/amd/fsp/picasso/FspsUpd.h
1 file changed, 11 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/48731/1

diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h
index 491ea47..48bd35f 100644
--- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h
+++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h
@@ -39,7 +39,17 @@
    /** Offset 0x0124**/	uint32_t                    gnb_ioapic_base;
    /** Offset 0x0128**/	uint8_t                     gnb_ioapic_id;
    /** Offset 0x0129**/	uint8_t                     fch_ioapic_id;
-	/** Offset 0x012A**/	uint8_t                     UnusedUpdSpace0[38];
+	/** Offset 0x012A**/	uint8_t                     UnusedUpdSpace0[6];
+	/** Offset 0x0130**/	uint8_t                     unused4[16];
+	/** Offset 0x0140**/	uint8_t                     DpPhyOverride;
+	/** Offset 0x0141**/	uint16_t                    EDpPhySel;
+	/** Offset 0x0143**/	uint8_t                     EDpVersion;
+	/** Offset 0x0144**/	uint8_t                     EDpTableSize;
+	/** Offset 0x0145**/	uint8_t                     DpVsPemphLevel;
+	/** Offset 0x0146**/	uint16_t                    MarginDeemPh;
+	/** Offset 0x0148**/	uint8_t                     Deemph6db4;
+	/** Offset 0x0149**/	uint8_t                     BoostAdj;
+	/** Offset 0x014A**/	uint8_t                     UnusedUpdSpace1[6];
    /** Offset 0x0150**/	uint16_t                    UpdTerminator;
 } FSP_S_CONFIG;