[coreboot-gerrit] [M] Change in coreboot[master]: drivers/intel/fsp2_0: Add saving MRC data after FSP-S option

[Jonathan Zhang (Code Review)]

Attention is currently required from: Simon Chou, Daocheng Bu, Johnny Lin, Subrata Banik, Arthur Heymans, Ray Han Lim Ng, Andrey Petrov.

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71950 )

Change subject: drivers/intel/fsp2_0: Add saving MRC data after FSP-S option
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Patch Set 3:

(1 comment)

File src/drivers/intel/fsp2_0/Kconfig:

https://review.coreboot.org/c/coreboot/+/71950/comment/3e03a276_a8687b8d 
PS2, Line 390:  MRC data compression/decompression can be done faster
             : 	  in memory than CAR due to larger data size.
> This is not true. The problem is that RAM is not cached when the MRC runs. […]

When MRC runs, the DRAM is not working yet. How would WB caching help?