Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61532 )
Change subject: soc/intel/apollolake: Rename PWRMBASE macro and function ......................................................................
soc/intel/apollolake: Rename PWRMBASE macro and function
This patch ensures PWRMBASE macro name and function to get PWRMBASE address on APL SoC is aligned with other IA SoC.
PMC_BAR0 -> PCH_PWRM_BASE_ADDRESS read_pmc_mmio_bar() -> pmc_mmio_regs()
Additionally, make `pmc_mmio_regs` a public function for other IA common code may need to get access to this function.
BUG=None TEST=None
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61532 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pmutil.c 6 files changed, 12 insertions(+), 9 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl index 7611a2d..b41a21a 100644 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -30,7 +30,7 @@ Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) - Store (PMC_BAR0, IBAS) + Store (PCH_PWRM_BASE_ADDRESS, IBAS)
CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 14e9b11..fe0cb93 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -62,7 +62,7 @@ pci_devfn_t pmc = PCH_DEV_PMC;
/* Set PMC base addresses and enable decoding. */ - pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); + pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS); pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 5e5b40e..e92227b 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,7 +25,7 @@ #define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14)
/* Accesses to these BARs are hardcoded in FSP */ -#define PMC_BAR0 0xfe042000 +#define PCH_PWRM_BASE_ADDRESS 0xfe042000 #define PMC_BAR1 0xfe044000 #define PMC_BAR0_SIZE (8 * KiB)
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index bc50b87..01efaff 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -235,6 +235,9 @@
void pch_log_state(void);
+/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + /* STM Support */ uint16_t get_pmbase(void);
diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 959fb53..4bb6229 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -15,7 +15,7 @@ int pmc_soc_get_resources(struct pmc_resource_config *cfg) { cfg->pwrmbase_offset = PCI_BASE_ADDRESS_0; - cfg->pwrmbase_addr = PMC_BAR0; + cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS; cfg->pwrmbase_size = PMC_BAR0_SIZE; cfg->abase_offset = PCI_BASE_ADDRESS_4; cfg->abase_addr = ACPI_BASE_ADDRESS; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 06c2d63..fbb2345 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -24,14 +24,14 @@
#include "chip.h"
-static uintptr_t read_pmc_mmio_bar(void) +uint8_t *pmc_mmio_regs(void) { - return PMC_BAR0; + return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; }
uintptr_t soc_read_pmc_base(void) { - return read_pmc_mmio_bar(); + return (uintptr_t)pmc_mmio_regs(); }
uint32_t *soc_pmc_etr_addr(void) @@ -153,7 +153,7 @@
void soc_fill_power_state(struct chipset_power_state *ps) { - uintptr_t pmc_bar0 = read_pmc_mmio_bar(); + uintptr_t pmc_bar0 = soc_read_pmc_base();
ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco2_sts = tco_read_reg(TCO2_STS); @@ -200,7 +200,7 @@
int vbnv_cmos_failed(void) { - uintptr_t pmc_bar = read_pmc_mmio_bar(); + uintptr_t pmc_bar = soc_read_pmc_base(); uint32_t gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1)); int rtc_failure = rtc_failed(gen_pmcon1);
4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.