Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63463 )
Change subject: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI ......................................................................
mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error.
What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs
This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S.
TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 --- A configs/config.msi_ms7d25 A src/mainboard/msi/ms7d25/Kconfig A src/mainboard/msi/ms7d25/Kconfig.name A src/mainboard/msi/ms7d25/Makefile.inc A src/mainboard/msi/ms7d25/bootblock.c A src/mainboard/msi/ms7d25/devicetree.cb A src/mainboard/msi/ms7d25/dsdt.asl A src/mainboard/msi/ms7d25/mainboard.c A src/mainboard/msi/ms7d25/romstage_fsp_params.c 9 files changed, 236 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63463/1
diff --git a/configs/config.msi_ms7d25 b/configs/config.msi_ms7d25 new file mode 100644 index 0000000..edcae72 --- /dev/null +++ b/configs/config.msi_ms7d25 @@ -0,0 +1,17 @@ +CONFIG_VENDOR_MSI=y +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/AlderLakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd" +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="adl-s_microcode.bin" +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_POST_DEVICE_PCI_PCIE=y +CONFIG_POST_IO_PORT=0x80 +CONFIG_SEABIOS_DEBUG_LEVEL=-1 diff --git a/src/mainboard/msi/ms7d25/Kconfig b/src/mainboard/msi/ms7d25/Kconfig new file mode 100644 index 0000000..7411d79 --- /dev/null +++ b/src/mainboard/msi/ms7d25/Kconfig @@ -0,0 +1,51 @@ +config BOARD_MSI_Z690_A_PRO_WIFI_DDR4 + select BOARD_MSI_MS7D25 + +config BOARD_MSI_MS7D25 + def_bool n + select SOC_INTEL_ALDERLAKE_PCH_S + select BOARD_ROMSIZE_KB_32768 + select SUPERIO_NUVOTON_NCT6776 + select DRIVERS_UART_8250IO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LPC_TPM + +if BOARD_MSI_MS7D25 + +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + +config MAINBOARD_DIR + default "msi/ms7d25" + +config MAINBOARD_PART_NUMBER + default "PRO Z690-A WIFI DDR4(MS-7D25)" if BOARD_MSI_Z690_A_PRO_WIFI_DDR4 + +config MAINBOARD_VENDOR + string + default "Micro-Star International Co., Ltd." + +config DEVICETREE + default "devicetree.cb" + +config DIMM_SPD_SIZE + default 512 + +config UART_FOR_CONSOLE + int + default 0 + +config USE_PM_ACPI_TIMER + bool + default n + +config USE_LEGACY_8254_TIMER + bool + default n + +config CBFS_SIZE + hex + default 0x1000000 + +endif diff --git a/src/mainboard/msi/ms7d25/Kconfig.name b/src/mainboard/msi/ms7d25/Kconfig.name new file mode 100644 index 0000000..05a8cee --- /dev/null +++ b/src/mainboard/msi/ms7d25/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_MSI_Z690_A_PRO_WIFI_DDR4 + bool "PRO Z690-A WIFI DDR4" diff --git a/src/mainboard/msi/ms7d25/Makefile.inc b/src/mainboard/msi/ms7d25/Makefile.inc new file mode 100644 index 0000000..2e6759f --- /dev/null +++ b/src/mainboard/msi/ms7d25/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/msi/ms7d25/bootblock.c b/src/mainboard/msi/ms7d25/bootblock.c new file mode 100644 index 0000000..cbadfb5 --- /dev/null +++ b/src/mainboard/msi/ms7d25/bootblock.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6687d/nct6687d.h> + +#define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Replicate vendor settings for multi-function pins in global config LDN */ + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + pnp_write_config(SERIAL_DEV, 0x15, 0xaa); + pnp_write_config(SERIAL_DEV, 0x1a, 0x02); + pnp_write_config(SERIAL_DEV, 0x1b, 0x02); + pnp_write_config(SERIAL_DEV, 0x1d, 0x00); + pnp_write_config(SERIAL_DEV, 0x1e, 0xaa); + pnp_write_config(SERIAL_DEV, 0x1f, 0xb2); + pnp_write_config(SERIAL_DEV, 0x22, 0xbd); + pnp_write_config(SERIAL_DEV, 0x23, 0xdf); + pnp_write_config(SERIAL_DEV, 0x24, 0x39); + pnp_write_config(SERIAL_DEV, 0x25, 0xfe); + pnp_write_config(SERIAL_DEV, 0x26, 0x40); + pnp_write_config(SERIAL_DEV, 0x27, 0x77); + pnp_write_config(SERIAL_DEV, 0x28, 0x00); + pnp_write_config(SERIAL_DEV, 0x29, 0xfb); + pnp_write_config(SERIAL_DEV, 0x2a, 0x80); + pnp_write_config(SERIAL_DEV, 0x2b, 0x20); + pnp_write_config(SERIAL_DEV, 0x2c, 0x8a); + pnp_write_config(SERIAL_DEV, 0x2d, 0xaa); + nuvoton_pnp_exit_conf_state(SERIAL_DEV); + + if (CONFIG(CONSOLE_SERIAL)) + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb new file mode 100644 index 0000000..dccaa25 --- /dev/null +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -0,0 +1,28 @@ +chip soc/intel/alderlake + device domain 0 on + device ref igpu on end + device ref crashlog off end + device ref xhci on end + device ref heci1 on end + device ref heci2 off end + device ref ide_r off end + device ref kt off end + device ref heci3 off end + device ref heci4 off end + device ref sata on end + device ref pcie_rp1 on end + device ref pcie_rp2 on end + device ref pcie_rp3 on end + device ref pcie_rp4 on end + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp7 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp10 on end + device ref pcie_rp11 on end + device ref p2sb on end + device ref hda on end + device ref smbus on end + end +end diff --git a/src/mainboard/msi/ms7d25/dsdt.asl b/src/mainboard/msi/ms7d25/dsdt.asl new file mode 100644 index 0000000..d3db0e1 --- /dev/null +++ b/src/mainboard/msi/ms7d25/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> +// #include <soc/intel/alderlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/msi/ms7d25/mainboard.c b/src/mainboard/msi/ms7d25/mainboard.c new file mode 100644 index 0000000..ac6b252 --- /dev/null +++ b/src/mainboard/msi/ms7d25/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +static void mainboard_init(void *chip_info) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c new file mode 100644 index 0000000..412e3ab --- /dev/null +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <soc/meminit.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistor FIXME */ + .resistor = 100, + + /* Baseboard Rcomp target values FIXME */ + .targets = { 50, 20, 25, 25, 25 }, + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_DESKTOP, /* FIXME */ + + .LpDdrDqDqsReTraining = 1, + + .ddr_config = { + .dq_pins_interleaved = false, /* FIXME */ + }, +}; + +static const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + .addr_dimm[1] = 0x51, + }, + [1] = { + .addr_dimm[0] = 0x52, + .addr_dimm[1] = 0x53, + }, + }, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); +}