[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Enable LPC generic IO decode range

[Johnny Lin (Code Review)]

Hello build bot (Jenkins), Andrey Petrov, Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth, Jonathan Zhang, David Hendricks, Jingle Hsu, Morgan Jang, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38994

to look at the new patch set (#10).

Change subject: soc/intel/xeon_sp: Enable LPC generic IO decode range
......................................................................

soc/intel/xeon_sp: Enable LPC generic IO decode range

To use Intel common block LPC function that enables the IO ranges
defined in devicetree.cb.

Tested on OCP Tioga Pass with BMC LPC working.

Signed-off-by: Johnny Lin 
Change-Id: I675489d3c66dad259e4101a17300176f6c0e8bd8
---
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/bootblock/bootblock.c
M src/soc/intel/xeon_sp/chip.h
M src/soc/intel/xeon_sp/include/soc/pcr_ids.h
M src/soc/intel/xeon_sp/lpc.c
5 files changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/38994/10