Hello Kyösti Mälkki, Aaron Durbin, Kane Chen, Aamir Bohra, V Sowmya, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34995
to look at the new patch set (#7).
Change subject: arch/x86: Cache the TSEG region at the top of ram ......................................................................
arch/x86: Cache the TSEG region at the top of ram
This patch adds new API for enabling caching for the TSEG region and setting up required MTRR for next stage.
BUG=b:140008206 TEST=Verified normal boot time on CML-Hatch with latest coreboot
Without this CL: Total Time: 929ms
With this CL: (TSEG marked as WB) Total Time: 910ms
For test marked TSEG as WP/WC: Total Time: ~920ms
Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar_loader.c 2 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/34995/7